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Hierarchical Rules Between "N" Levels of Packaging

IP.com Disclosure Number: IPCOM000106306D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 6 page(s) / 284K

Publishing Venue

IBM

Related People

Selinger, CR: AUTHOR [+2]

Abstract

Described are hierarchical rules and how they are used toallow for contained rules changes for a given level of packaging. Prior methodologies required one rule to span multiple levels of packaging for a complete source to sink circuit. If any of the requirements or electrical characteristics of one of the packaging levels were to change, all of the packages would need to be re-verified. Hierarchical rules allow for full verification of all requirements or electrical characteristics changes totally contained within the individual level of packaging that the change addresses.

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Hierarchical Rules Between "N" Levels of Packaging

      Described are hierarchical rules and how they are used toallow
for contained rules changes for a given level of packaging.  Prior
methodologies required one rule to span multiple levels of packaging
for a complete source to sink circuit.  If any of the requirements or
electrical characteristics of one of the packaging levels were to
change, all of the packages would need to be re-verified.
Hierarchical rules allow for full verification of all requirements or
electrical characteristics changes totally contained within the
individual level of packaging that the change addresses.

      The concept of hierarchical rules was first introduced in 1981
by the authors.  The SHUFFLE Package Designhas been successfully used
to produce the IBM 3090* and the IBM ES/9000* package designs.
Hierarchial rules allow packages to be designed based on that
specific package.  This concept allows a package to be unaffected by
changes to urles regarding nets that are only partially on the
current package in question.  This allows for a more streamlined
design.

      The package wiring rules contain the pin type definitions, the
interconnection rules, and the electrical parameter limits.  This
rule is composed of two parts, the pin definitions and the
interconnection/electrical rules.  The pin definitions include all
the pertinent data for all of the pins in the current technology
system and package level.  The interconnection/electrical rules
define how various types of pins can be connected between components
on a package and to component I/Os.

      In order to transform current technology rules into SHUFFLE
package wiring rules, "standard" information is required.  The data
available within the technology definition must be consistent with
the data requirements of the SHUFFLE package wiring rules.  A
technologist who needs to generate wiring rules can choose virtually
any format he wishes.  The wiring rules developer needs to know the
rule format required.  From this information the ASTAP model and
analysis to generate rules in the required format can be shaped.

      The pin data records contain the pin specifications.  Each pin
carries with it enough detailed information to satisfy the needs of
all package analysis functions that deal directly with pins.
Comments may be placed anywhere within or around the pin data
records.  The format of the pin data records is as follows:

COLUMNS   DESCRIPTION

1 to 3    Pin type specification, not related to this paper.

5 to 8    The pin type will take on different meanings depending
          on the level of packaging you are developing.  If you are
on an

          LLP (lowest level package) with chips directly mounted on
it,
          the pin field will contain a pin type name.  Some examples
of
          lowest level packages are TCMs, SCMs, and MCMs with chips
          dir...