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64x64x2 Hardware Sprite Overlayed on VRAM Serial Data

IP.com Disclosure Number: IPCOM000106308D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 120K

Publishing Venue

IBM

Related People

Arroyo, RX: AUTHOR [+3]

Abstract

Provided is a hardware sprite on the low-cost graphics adapter which uses an inexpensive DAC (SPD2). The SPD2 does not have a hardware sprite function and does not provide input pin control for data overlay.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

64x64x2 Hardware Sprite Overlayed on VRAM Serial Data

      Provided is a hardware sprite on the low-cost graphics adapter
which uses an inexpensive DAC (SPD2).  The SPD2 does not have a
hardware sprite function and does not provide input pin control for
data overlay.

        The product requires a low-cost, small-footprint graphics
adapter (SGA).  The SGA provides a 64x64 pixel, by 2 color sprite
that is implemented in the hardware.  To keep the cost down, the SPD2
(Serialiser/Pallette/DAC)module is utilized; while this modules
provides several features, it does not provide a hardware sprite
function that is commonly found in much more expensive external
RAMDAC's.  Consequently, the sprite data must be overlayed on the
VRAM serial data before presented to the SPD2.

      The SGA consists of two inexpensive ASICs, the VRAM frame
buffer, and the SPD2.  Chip #2 contains a 1 KByte (64x64x2bit sprite)
RAM macro and the control logic to overlay the sprite data on the
VRAM serial data.  This chip takes the serial data and generates the
video data that is ultimately clocked into the SPD2 as video data.

      Fig. 1 is an overview of the graphics adapter.  The SPD2
outputs a signal called VRCLK, which is used to clock the VRAM serial
port, and expects an input clock called VRCLKRTN, which is a
synchronized version of VRCLK.  The chip uses VRCLK to clock the
sprite overlay control logic.  VRCLKRTN is used by SPD2 to clock in
video data.

      Fig. 2 shows a high-level diagram of the overlay control logic.
The SPD2 video data interface is 32-bit wide, 4 pixels.  The SPD2 is
programmed for 8 bits per pixel.  Chip #2 handles the data
manipulation to support the different video modes (i.e., 1 bit/pixel,
4 bit/pixel, and 8 bit/pixel).  This allows for all 8 bits of the
sprite color registers, CURCOL, to be presented to the SPD2
regardless of the video mode.

      The sprite may be positioned with pixel resolution on the
screen, thus the sprite data must be shifted to be aligned with the
video data.  This function is implemented in the `Shift Muxing'
block, and is controlled by `Shift/Align' block.

      The `Shift Mas...