Browse Prior Art Database

Near-Custom Book Image

IP.com Disclosure Number: IPCOM000106333D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 171K

Publishing Venue

IBM

Related People

Grohoski, GF: AUTHOR [+3]

Abstract

This invention provides a standard cell image for VLSI design that allows individual device size tuning. This tuning achieves performance comparable to custom circuit design without giving up the short design schedule of standard cell design.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 49% of the total text.

Near-Custom Book Image

      This invention provides a standard cell image for VLSI design
that allows individual device size tuning.  This tuning achieves
performance comparable to custom circuit design without giving up the
short design schedule of standard cell design.

      Conventional standard cell design uses a set of predesigned
circuit blocks with assorted logical functions (NAND, NOR, etc.).
These are assembled and wired together to form a specific high-level
logic function.

      Each block contains devices of fixed size.  Performance tuning
is done by choosing blocks that have larger or smaller devices.
Unfortunately,   the number of combinations of input device and
output device sizes is extremely limited so as to keep the size of
the library manageable.  A small six way NAND will have only small
input and output devices.  A large NAND will have only large inputs
and a large output.  Combinations  of large and small inputs are not
provided because of the huge number of  block designs that would need
to appear in the library.

      Gate capacitance is the major contributor to CMOS capacitance
and therefore to CMOS circuit delay.  The lack of custom tuned device
sizes means that standard cell designs must have significantly lower
performance that custom designs.

      A more sophisticated standard cell approach involves
`parameterized' blocks.  A few general form logic blocks exist in the
library, and specific device sizes are drawn to suit each instance of
a block in a particular design.  Unfortunately, the standard cell
circuit image must place a lower limit on allowed device size or give
up density.  The contacts for power and personalization wiring
require diffusion borders which must extend under the gate (Fig. 1).
There are 3-4 wiring tracks worth of these contacts and their
diffusion borders force a minimum device size of 3-4 tracks.  Since
minimum device size is 1 track, most of the tuning range for device
size is unavailable.  Spacing apart the gates enough for borders and
narrow devices reduces the density of the standard cell image (Fig.
2).

      A standard cell image is disclosed that exploits a salicide
wiring layer to allow custom tuned device sizes with no loss in
density.  This image allows for continuous device width tuning across
added fingers with no discontinuity in available width.  Individual
device tuning gives this standard cell image a performance comparable
to custom design.

      Fig. 3 illustrates a standard cell layout with infinite device
size tuning and no loss of density.  Polysilicon (PC) wires lie
across diffusion (RX) to form FETs as is the usual practice.
Salicide (MC) strips lie between the gates (PC).  Connections from
power and personalization wires are made to the MC strips.  The MC
strips require such a small RX border that no incursion into the gate
area is required.  RX is added in the gate area to create the desired
transistor width...