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Differential Analog to Digital Signal Converter

IP.com Disclosure Number: IPCOM000106347D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Neff, RM: AUTHOR [+3]

Abstract

The invention is an analog to digital converter (DAC) useful in converting a pair of low level analog input signals having a 180 degree phase shift with respect to each other, into a pair of high-level digital signals having a precisely defined cross-voltage at approximately 50% of their rise/fall time. Thus, no phase shift occurs in the output signals other than that occurring between the input signals.

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Differential Analog to Digital Signal Converter

      The invention is an analog to digital converter (DAC) useful in
converting a pair of low level analog input signals having a 180
degree phase shift with respect to each other, into a pair of
high-level digital signals having a precisely defined cross-voltage
at approximately 50% of their rise/fall time.  Thus, no phase shift
occurs in the output signals other than that occurring between the
input signals.

      The output of a first inverter INV1 is coupled to its input and
to the negative input of an operational amplifier.  The output
voltage of INV1 is equal to the transition voltage V(tr) of the
inverter.  Thus both inputs to the op amp are driven to V(tr).

      The positive input of the op amp is coupled to a common node
between serially connected transistors T1 and T2, thus driving this
node voltage to V(tr).  The output of the op amp, V(op), provides the
gate voltage to T1.  The gate voltage of T2 is V(c), and it follows
that the gate source voltage of T2 is [V(c) - V(tr)].

      The T1/T2 serial device configuration is twice duplicated by
configurations T1'/T2' and T1''/T2''.  (Devices T1, T1' and T1'' are
identical.  Similarly, devices T2, T2' and T2'' are identical).
V(op) provides  the gate voltage to T1' and T1''.  The gate voltages
to T2' and T2'' are V(i) and inverse V(i), respectively.

      The common node between T1' and T2' is coupled to the input of
a second inverter IN...