Browse Prior Art Database

Boundary Scan Descriptive Language for Non-JTAG Components

IP.com Disclosure Number: IPCOM000106362D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Heybruck, W: AUTHOR [+2]

Abstract

Described is a method for writing Boundary Scan Descriptive language (BSDL) to describe a component that does not comply with the IEEE 1149.1 standard. This method is useful when one wants to create automatic test pattern generator (ATPG) interconnect tests for a card that contains both devices that are standard-compliant and devices that are not standard-compliant. These devices are referred to as JTAG and non-JTAG devices, respectively.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Boundary Scan Descriptive Language for Non-JTAG Components

      Described is a method for writing Boundary Scan Descriptive
language (BSDL) to describe a component that does not comply with the
IEEE 1149.1 standard.  This method is useful when one wants to create
automatic test pattern generator (ATPG) interconnect tests for a card
that contains both devices that are standard-compliant and devices
that are not standard-compliant.  These devices are referred to as
JTAG and non-JTAG devices, respectively.

      A BSDL file for each component on a card, along with the card's
netlist, are the inputs a tester uses to generate test patterns.  The
BSDL file describes a component's pin connections, its Test Access
Port, its test instruction set, and its boundary scan register.  The
Test Access Port, instructions, and boundary scan register are
expected to be standard-compliant.  However, a non-JTAG device 1)
will not have a Test Access Port, 2) will not use the standard's
instruction set, or even a test instruction register, and 3) will
probably not have standard-compliant boundary scan register cells.
By using the method described to write BSDL for the non-JTAG device,
these three deviations from the standard can be masked so that
appropriate interconnect test patterns for the component can be
written by the ATPG program.

The non-JTAG device "appears" standard-compliant when the following
modifications are made to the BSDL:

1.  The "Scan Port Identification" section, which describes the Test
    Access Port,  instead describes the test pins used by the
    non-JTAG device.  These would typically be a scan-in and scan-out
    line for the non-JTAG boundary scan register, a reset line, and a
    clock.  For a Level Sensitive Scan Design (LSSD) component, t...