Browse Prior Art Database

Subsystem Control Block/Direct Memory Access Design for Personal Computers

IP.com Disclosure Number: IPCOM000106373D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 6 page(s) / 263K

Publishing Venue

IBM

Related People

Amini, N: AUTHOR [+5]

Abstract

Described is an architectural logic implementation designed to increase operational performance of personal computer (PC) systems. The design enables subsytem control block (SCB) initiated direct memory access (DMA) transfers to proceed without involving the central processing unit (CPU).

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Subsystem Control Block/Direct Memory Access Design for Personal Computers

      Described is an architectural logic implementation designed to
increase operational performance of personal computer (PC) systems.
The design enables subsytem control block (SCB) initiated direct
memory access (DMA) transfers to proceed without involving the
central processing unit (CPU).

      In prior art, DMA transfers were all programmed by the CPU
using input/output (I/O) write operations to the DMA circuitry.  All
of the parameters of a DMA transfer, such as source and destination
addresses, and transfer count, were written one byte at a time to the
DMA by the CPU.  This prior art method affected overall operational
performance because of the CPU involvement.

      The concept described herein improves processing performance by
using SCB functions to pass control information between devices that
use shared memory.  The DMA utilizes the SCBs stored in memory, by
the CPU or a bus master, as a way of programming the DMA transfer.
This allows the parameters of the DMA transfer to be read in by the
DMA itself and to use fast memory read cycles to gather the
information.  The CPU only needs to inform the DMA that it is an SCB
initiated transfer so that the DMA can take over.  The CPU can then
continue to perform other tasks, instead of using I/O cycles to
program the DMA.  Using the SCB to program the DMA transfer off loads
much of the work of programming the DMA transfer from the CPU and
enables the DMA to gather the information needed to execute a DMA
transfer.  This provides a performance gain over the prior art method
of programming the DMA transfer with I/O write operations from the
CPU.

      The following illustrates the logic to support the subsytem
control blocks when added to a thirty-two bit DMA design.  The SCB
support logic shares the logic with the DMA section.  The DMA and the
SCB sections share the central control RAM (random access memory)
(CCR), main state machine, address2 incrementer/decrementer, transfer
count counter and the first-in-first-out (FIFO) buffer.  This logic
sharing allows for the adding of the SCB support in less space and
utilizes the circuits more efficiently, than in the prior art design.

      The SCB support logic includes a SCB execution state machine
which encompasses byte enable generation logic and SCB counter logic.
The DMA and the SCB logic sections share the DMA main state machine,
which includes; the CCR, the FIFO buffer, the DMA address2 logic and
the DMA transfer count logic.

      In a SCB initiated DMA transfer, a control block is stored into
memory by the CPU, or a bus master.  If the SCB is using data
chaining, an indirect list (IList) is also stored into memory.  A
control block is typically sixteen bytes in length.  Fig. 1a shows a
block diagram format of the SCB without the indirect list and Fig. 1b
shows a block diagram format for the SCB with the indirect list. ...