Browse Prior Art Database

Boundary Walking Sequences for Circuit Board Interconnect Test

IP.com Disclosure Number: IPCOM000106383D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 220K

Publishing Venue

IBM

Related People

Chan, JC: AUTHOR [+3]

Abstract

A new technique is described to automate the interconnect wiring test, which is performed as part of the Power-On Self-Test (POST) at the manufacturing stage. Essential to the implementation is the idea of response compression using the Multiple Input Signature Registers (MISR). Interconnect wiring defects are diagnosed by comparing the content of the MISR with the expected result after a simple test procedure. As a result, the proposed technique has the advantages of low overhead cost and easy fault detection.

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Boundary Walking Sequences for Circuit Board Interconnect Test

      A new technique is described to automate the interconnect
wiring test, which is performed as part of the Power-On Self-Test
(POST) at the manufacturing stage.  Essential to the implementation
is the idea of response compression using the Multiple Input
Signature Registers (MISR).  Interconnect wiring defects are
diagnosed by comparing the content of the MISR with the expected
result after a simple test procedure.  As a result, the proposed
technique has the advantages of low overhead cost and easy fault
detection.

      Because Boundary Scan test is serial, it is important to
minimize the number of test vectors while maintaining the fault
detection and diagnostic resolution.  This has renewed interest in
exploring efficient test algorithms and implementation techniques.
Here, we propose a scheme of implementation using response
compression as shown in the Figure.

      In board level testing, response compression is a well known
method of reducing test data volume by compressing the output
responses of the device under test.  Defects are detected by
comparing the compressed response (signature) with the expected
result from simulation or the "golden" unit.  Here, the idea is to
modify the existing boundary scan path so that it has the function of
responses compression (MISR) in addition to the shift operation.

With this new capability, the test procedure will be composed of two
steps.

1.  The test patterns are delivered serially by operating the shift
    registers in the scan mode.  Now, the response of the network
    during each test cycle is captured and compressed into the MISR
    formed by the boundary registers on the receiver side.

2.  At the completion of step (1), if an incorrect signature is
    observed (content of the MISR registers), the presence for
    fault(s) is detected.  Further, the analysis of the error
    signature can provide information of generating the additional
    test patterns for fault isolation when greater diagnostic
    resolution is desired.

      In contrast, if the signature from the response compression is
as expected, the subsequent test operations can be avoided, which
requires much more time and data storage volume.

      Note, both steps (1) and (2) can be completed as part of the
Power-On Self-Test running at system speed.  The justification for
such a modification is discussed qualitatively next.  From a high
level perspective, shifting is the most time consuming part of
traditional Boundary Scan Testing.  The application of each test
pattern requires a sequence of serial shift operations to deliver the
test vector.  During the setup process, no information from the
responses of the wiring interconnect is captured, even though many
different excitation patterns have passed through the inputs.  Only
the response to the targeted test vector is captured, all the
transi...