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Browse Prior Art Database

Mechanism for High Speed Context Switch

IP.com Disclosure Number: IPCOM000106423D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Tago, K: AUTHOR

Abstract

Disclosed is a software mechanism to implement high performance process dispatch.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 59% of the total text.

Mechanism for High Speed Context Switch

      Disclosed is a software mechanism to implement high performance
process dispatch.

      The process dispatcher is a component of operating system
kernel.  It implements context switch between processes.  The context
switch is implemented by the following sequence:

1.  Save current context to a context save are of current process.
    That is done by storing contents of hardware registers to the
    save area which is placed in the main memory.

2.  Resume the context of the process to be executed next.  That is
    done by loading values of hardware registers from the save area.
    The values are saved by the previous context switch.

      When the context switch is performed frequently, the overhead
by saving and loading number of registers becomes an issue.

      The problem can be alleviated by the selective context save and
resume.  The number of registers which are to be saved and resumed at
context switch time depends on process types.  Existing dispatcher
saves and resumes maximum set and fixed number of registers
regardless of process types.  If a dispatcher saves and resumes the
precise number of registers, the overhead of context switch can be
reduced.  The invention provides the mechanism to save ant resume
variable number of register values.

      A dispatcher which is implemented by using the invention
implements the context switch as follows:

1.  Jump to one of routines...