Browse Prior Art Database

Pillar Dram Cell With Dual Channels and an Underneath Trench-in-Trench Capacitor Built on Soi Structure

IP.com Disclosure Number: IPCOM000106426D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 95K

Publishing Venue

IBM

Related People

Wu, B: AUTHOR

Abstract

Disclosed is a pillar-like DRAM cell having a dual-channel vertical transistor built on SOI and a trench-in-trench capacitor formed underneath the transistor. DRAM density is improved because the transistor is on the top of capacitor. DRAM performance is enhanced because of the dual channels, SOI structure and large capacitance.

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Pillar Dram Cell With Dual Channels and an Underneath Trench-in-Trench Capacitor Built on Soi Structure

      Disclosed is a pillar-like DRAM cell having a dual-channel
vertical transistor built on SOI and a trench-in-trench capacitor
formed underneath the transistor.  DRAM density is improved because
the transistor is on the top of capacitor.  DRAM performance is
enhanced because of the dual channels, SOI structure and large
capacitance.

      Density and performance are two major concerns in designing
DRAM cells.  Scaling down the cell size is the conventional approach
to increase the DRAM density, which usually involves with complicated
process steps, sophisticated lithography tools, long development time
and thus high cost and risk.  While scaling down the cell size, a
minimal capacitance value has to be maintained To ensure proper
functionality of DRAM cell, This criterion will further increases the
process complexity (such as multiple-layer stacked capacitor) or
difficulty (such as deep trench capacitor).  To improve the DRAM
performance, a high performance transistor (high trans-conductance,
low parasitic capacitance,...) and a low leakage capacitor are
inevitable.  A typical way to enhance transistor performance is to
scaled down the transistor vertically and laterally, which again
requires complicated process methods (such as thin gate oxide,
shallow S/D junction,...for vertical scaling) and expensive
lithographic tools (such as short gate length, tight overlay design
rules,...for lateral scaling).

      Disclosed is a pillar-like DRAM cell having a dual-channel
vertical transistor built on SOI and a trench-in-trench capacitor
formed underneath the transistor (Fig. 1).  Building the transistor
on the top of trench capacitor can increase the DRAM density and thus
enable a trench-in-trench capacitor to be used without increasing the
cell size.  The novel features and the advantages of the cell
proposed a...