Browse Prior Art Database

Method for Eliminating Read/Write Setup Microprocessor

IP.com Disclosure Number: IPCOM000106448D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 115K

Publishing Venue

IBM

Related People

Hicken, MS: AUTHOR [+2]

Abstract

A method for reducing read/write set-up time for the microprocessor overhead within a Direct Access Storage Device. This invention provides an implementation of allowing a read or write operation to begin immediately after the completion of the servo access to the data location.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 46% of the total text.

Method for Eliminating Read/Write Setup Microprocessor

      A method for reducing read/write set-up time for the
microprocessor overhead within a Direct Access Storage Device.  This
invention provides an implementation of allowing a read or write
operation to begin immediately after the completion of the servo
access to the data location.

      This invention can be applied equally to either single or
multiple microprocessor implementations of a DASD controller.  The
following example illustrates the implementation for a DASD
controller that uses two microprocessors.  The first microprocessor
will be referred to as the Interface Processor (IP).  The second
microprocessor will be referred to as the Servo Processor (SP).

      This invention can also be applied equally to an implementation
that does not use sector IDs to locate the desired sector.  For these
types of implementations, the sector to be accessed may be known
prior to accessing the track.  While the actual detailed
implementation of this invention may vary for these two cases, the
concept and intent of the invention remains the same.  The following
example illustrates an implementation that does use sector IDs to
locate the desired sector on a track.

      Before this invention, the typical sequence of events while
executing a read or write operation was as follows:

1.  IP receives a READ or WRITE command from a host controller

2.  IP decodes the command and determines the track to access

3.  IP communicates a Seek command to the SP

4.  SP begins seeking to the desired track

5.  IP initializes some hardware registers in parallel with seek

6.  SP completes the seek operation

7.  SP communicates to IP that Seek is complete

8.  IP detects that SP has completed seek

9.  IP completes setup of Read/Write Disk Controller hardware

10. IP starts the hardware logic to search for the correct sector

11. IP waits for the hardware to complete the sector read or write
    operation

      This invention eliminates the "Setup Read/Write Transfer
Overhead" that is defined as steps 7 through 10 in this example.

The following new hardware functions are included in this invention:

o   An IP control register bit that:

    -   When equal to 0, signals the hardware that a read operation
        is not allowed.

    -   When equal to 1, signals the hardware that a read operation
        is allowed.

o   An SP control register bit that:

    -   When equal to 0, signals the hardware that a read operation
        is not allowed.

    -   When equal to 1, signals the hardware that a read operation
        is allowed.

o   A digital logic function which controls whether a read operation
    is actually allowed to occur.  A read operation is only allowed
    if both the IP and SP control signals are set to 1.  This digital
    logic contains the following inputs, outputs, and functions:

    -   Inputs:

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