Browse Prior Art Database

Verification Test Injection Logic for Clock Missing Pulse Detector

IP.com Disclosure Number: IPCOM000106464D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 128K

Publishing Venue

IBM

Related People

Meaney, PJ: AUTHOR [+2]

Abstract

This invention provides for the AC testing of clock trees for the 3090H5 project. It also allows the clock checking logic itself to be checked out prior to shipping machines. Finally, it allows isolation of AC defects by clock tree.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Verification Test Injection Logic for Clock Missing Pulse Detector

      This invention provides for the AC testing of clock trees for
the 3090H5 project.  It also allows the clock checking logic itself
to be checked out prior to shipping machines.  Finally, it allows
isolation of AC defects by clock tree.

      The 3090H2 project had implemented Missing Pulse Detector (MPD)
logic to detect for Stuck and Intermittent Stuck faults on clocks.
This logic resided on all the clock powering chips (JC1).

      To test this logic, the clocks had to all be stopped at known
states.  Then the JC1 was scanned to force the output checker to flip
(logic '1' to logic '0' or vice versa).  This procedure allowed
faults between the output of the JC1 chip and the input of the Error
Reporting Register (ERR) to be detected.

However, there was no test to detect defects within the MPD logic
itself.

      The Missing Pulse Detector was implemented for the first time
on the 3090H2 machines.  The function was disabled for the 3090H2.

      Each clock chip has 18 clock trees (labeled A1,B1,...J1,A2,B2,
All clock trees have a Missing Pulse Detector (MPD) circuit which
will detect one or more missing clock pulses.  The MPD function
samples a clock at ten, evenly-distributed time periods.  A clock is
considered defective if all ten samples are either logically zero or
logically one.  Otherwise, the clock is assumed to be switching
normally.

      The logical implementation of the MPD function for one clock
tree is shown in Fig. 1.  The clock tree gets propagated through nine
levels of delay.  This yields ten sample signals.  These signals are
NOR-ed and AND-ed as shown.

      The detector outputs from the 18 above clock trees are then
Exclusive-OR-ed together to yield MPD_EVEN$ and MPD_ODD$.  This is
shown in Fig. 2.  The MPD_EVEN$ signal will be active when an EVEN
number of clock trees are running.  The MPD_ODD$ signal will be
active when an ODD number of clock trees are running.  The MPD
function can detect if an ODD number of clocks are defective.

      The 3090H2 VT logic consists of a Shift Register Latch (SRL),
CLK_VT_SRL, in addition to a controlling input, VT_TEST.  The VT_TEST
input is held logically high to disable the VT function.  This allows
scanning of the controlling SRLs.

The VT test consisted of performing the following operations:

1.  VT_TEST is normally high.

2.  Stop all clocks.

3.  Scan VT SRL to ZERO.

4.  Drop VT_TEST.  Allow errors (if any) to propagate.

5.  Raise VT-TEST.

6.  Scan VT SRL to ONE.

7.  Drop V_TEST.  Allow errors (if any) to propagate.

      Normally, the ten samples for the A1 tree are all stuck at
logical ZERO.  The VT SRL is then used to toggle one input of the
NOR.  This causes the MPD EVEN and ODD outputs to switch.  The error
will then propagate to the Error Reporting Register.

      The purpo...