Browse Prior Art Database

Design/Structure of Stud Via in the Internal Layer

IP.com Disclosure Number: IPCOM000106468D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Terada, K: AUTHOR [+2]

Abstract

Disclosed is a structure of Stud via design in the PCB (Printed Circuit Board) in order to make the reliability of a via connection higher.

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Design/Structure of Stud Via in the Internal Layer

      Disclosed is a structure of Stud via design in the PCB (Printed
Circuit Board) in order to make the reliability of a via connection
higher.

      When Stud via is used to make a connection of, for example,
Stud via on the two circuit layers (Fig. 1), the Stud via is designed
so that the size of both Studs are same and the entry line does not
have a land.  This structure has a demerit that the mechanical stress
is concentrated on the connection point between the Stud via barrel
and entry line.  This stress becomes stronger when the number of the
connection layer increases.

      In order to relief the mechanical stress concentration at
position, the Stud via structure is designed so that the both upper
and lower Studs have a different edge.  The physical design example
is shown in Fig. 2.  Fig. 3 also shows the design that the land which
is bigger than the Stud is placed at the end of the circuit for the
same purpose.

These structures of Stud via design have a higher reliability of the
connection.