Browse Prior Art Database

Dynamic Circuit Implementation for Control Logic

IP.com Disclosure Number: IPCOM000106479D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 97K

Publishing Venue

IBM

Related People

Borkenhagen, JM: AUTHOR

Abstract

Existing dynamic circuit design techniques work well for data flow logic but not for control logic. Reconvergent paths and multiple path lengths that normally exist in control logic present special problems to the dynamic circuit designer. An effective and simple dynamic circuit implementation for control logic design is disclosed.

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Dynamic Circuit Implementation for Control Logic

      Existing dynamic circuit design techniques work well for data
flow logic but not for control logic.  Reconvergent paths and
multiple path lengths that normally exist in control logic present
special problems to the dynamic circuit designer.  An effective and
simple dynamic circuit implementation for control logic design is
disclosed.

      Two copies of timing critical control logic are implemented
with dynamic CMOS circuits.  Fig. 1 displays a domino CMOS circuit
that can be used for this implementation, but other dynamic circuits,
such as DCVS, and other technologies, such as BiCMOS, work equally as
well.  The inputs to the dynamic logic shown in Fig. 2 come from
static latch outputs.  The outputs of the two copies of dynamic logic
feed into a static multiplexor.  The static multiplexor can feed
directly into a static latch or into more static logic.  The two
copies of dynamic logic are precharged and evaluated on alternate
processor clock cycles as displayed in Fig. 3.  The logic copy that
is being evaluated is selected at the multiplexor during normal
operation.

      This application of dynamic circuits in control logic is done
without complex precharge clocks, clock skew penalties, or dead cycle
time normally created by precharging and without the need to balance
path lengths at convergence points.

      Dynamic circuits reduce the timing delay of control logic
compared to a standard static CMOS implementation.  Dynamic circuit
delay is dependent on N-FETs during the evaluation phase while static
circuit delay is dependant on P-FETs, which are inherently slower for
the same-sized device.  Both N-FETs and P-FETs add to the input
capacitance on static circuits.  Input capacitance on dynamic
circuits is from only N-FETs.  The reduced input capacitance of
dynamic circuits results in better delay performance.

      Area used to implement control logic with dynamic CMOS is less
than with static CMOS logic because of the reduced number of P-FETs
in dynamic logic, but the area savings is offset by th...