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Digital Filter with Dual-Table Look-Up Multiply

IP.com Disclosure Number: IPCOM000106485D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 109K

Publishing Venue

IBM

Related People

Harr, J: AUTHOR

Abstract

By using an Analog-to-Digital Converter (ADC) with a "sign plus magnitude" coded output, the coefficient multiplications needed in a digital filter can be done with a simple dual-table look-up technique using only four registers, instead of the sixteen registers needed with the usual method.

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This is the abbreviated version, containing approximately 52% of the total text.

Digital Filter with Dual-Table Look-Up Multiply

      By using an Analog-to-Digital Converter (ADC) with a "sign plus
magnitude" coded output, the coefficient multiplications needed in a
digital filter can be done with a simple dual-table look-up technique
using only four registers, instead of the sixteen registers needed
with the usual method.

      Digital Filters that take their outputs from ADCs sometimes use
a dual-table look-up multiply, wherein the low-order bits of the ADC
address a RAM or registers to look up a first partial product, and
the high-order bits of the ADC address another RAM or registers to
produce a second partial product.  These partial products are then
added to produce the final result.  If a six-bit ADC is used, the
low-order three bits would be used to address eight low-order
registers, and the upper three bits would likewise address eight
other registers, for a total of sixteen registers required.

      If "sign plus magnitude" coding is used for the ADC output
instead of the usual "twos complement" coding, a substantial
simplification of the multiplier can be obtained.  The Figure shows
the disclosed multiplier with a six-bit ADC assumed.  As shown in the
Figure, only four registers are needed.  If the letter "k" represents
the value of the coefficient (multiplicand), then registers 7-10 need
only store the values k, 3k, 5k and 7k.

      The registers 7-10 are connected to multiplexer 14 in such a
way that any of the values 0k, 1k, 2k, ..., 7k may be obtained at the
output of multiplexer 14.  To illustrate, the output of register 8
(holding the value 3k) is connected directly to the "3k" input of
multiplexer 14.  But the value of 6k is simply the value of register
8 shifted left by one binary place, multiplying its value by two.  So
register 8 is connected to the "6k" input of multiplexer 14 with a
left shift of one binary place to all the output lines of register 8,
so that when the multiplexer switches the output to that "6k" input,
the value of 6k appears at the output 15.  In a similar manner,
register 7's output is connected into the "2k" input of multiplexer
14 with a one-place shift to provide 2k, and into the "4k" input with
a two-place shift to provide 4k.  In this manner, when control input
16 has the values 0, 1, 2, ..., 7 then output 15 will have the values
0, 1k, 2k, ..., 7k, providing the product of the control value and k.

      In a similar manner, when control 13 has the values 0, 1, 2, 3,
the output 12 of multiplexer 11 will have the values 0, 8k, 16k, 24k,
because the output of register...