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Browse Prior Art Database

Mechanism for Testing Off-Chip Memory

IP.com Disclosure Number: IPCOM000106490D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 81K

Publishing Venue

IBM

Related People

Burmeister III, WF: AUTHOR

Abstract

Disclosed is a hardware mechanism that assists with the testing of an external memory array. The mechanism executes repetitive array test primitives on command from array test software. This mechanism allows the array test strategy and test algorithms to be embodied in software, while the array test executes at hardware speeds. Consequently, the array test implementation has the benefits of a pure software test that can be improved as manufacturing and field defect data is gathered, and has the reduced execution time benefit of a pure hardware array test.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Mechanism for Testing Off-Chip Memory

      Disclosed is a hardware mechanism that assists with the testing
of an external memory array.  The mechanism executes repetitive array
test primitives on command from array test software.  This mechanism
allows the array test strategy and test algorithms to be embodied in
software, while the array test executes at hardware speeds.
Consequently, the array test implementation has the benefits of a
pure software test that can be improved as manufacturing and field
defect data is gathered, and has the reduced execution time benefit
of a pure hardware array test.

      The mechanism can be used to test memory arrays composed of
SRAM modules, DRAM modules, and with the addition of a second data
port, Video RAMs.

      The mechanism shown in the figure is controlled by the Array
Test State Machine.  Some typical operating modes of the Array Test
State Machine are listed below with a corresponding sequence of
operations for each mode.

Read Array                                 Write Array

     1.  Read array                              1.  Write array

     2.  Compare pattern                         2.  Next pattern

     3.  Next pattern                            3.  Next address

     4.  Next address

Write/Read Array                           Read/Write/Read Array

     1.  Write array                             1.  Read array

     2.  Read array                              2.  Compare pattern

     3.  Compare pattern                         3.  Next pattern

     4.  Next pattern                            4.  Write array

     5.  Next address                            5.  Read array

                                                6.  Compare pattern

                                                7.  Next pattern

                                       ...