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Browse Prior Art Database

Arbitration History Buffer

IP.com Disclosure Number: IPCOM000106491D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 96K

Publishing Venue

IBM

Related People

Haess, J: AUTHOR [+3]

Abstract

The bring-up and verification of a microprocessor system is a difficult task although processors provide some means for analysis, measurement, tracing and error stops. In particular when asynchronous I/O (Input/Output) operations arise such analysis gets much more difficult as it is hard to find out which I/O-operations have already finished and which ones are still running. Those problems increase dramatically with multi-tasking and multiprocessing, as the systems are getting more and more complex and several resources are sharing the same devices. Disclosed is method used to simplify the analysis of the actual status of the system to trace the last operations that were done before the problem occurred.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Arbitration History Buffer

      The bring-up and verification of a microprocessor system is a
difficult task although processors provide some means for analysis,
measurement, tracing and error stops.  In particular when
asynchronous I/O (Input/Output) operations arise such analysis gets
much more difficult as it is hard to find out which I/O-operations
have already finished and which ones are still running.  Those
problems increase dramatically with multi-tasking and
multiprocessing, as the systems are getting more and more complex and
several resources are sharing the same devices.  Disclosed is method
used to simplify the analysis of the actual status of the system to
trace the last operations that were done before the problem occurred.

      The apparatus used identifies the sources as well of the sinks
of these operations.  It allows each I/O bus arbiter to control the
recording of the last originators of I/O operations with the
appropriate Bus-Unit-IDs together with the issued command.  The
arbiter therefore decodes its own one-of-n Grant-mechanism into a
more compact binary code and stores this into a special arbitration
history buffer together with the command coming from the granted
Bus-Unit.  The buffer used is a first-in-first-out buffer (FIFO) and
the number of records of operations that can be stored is dependent
on the size of the buffer.  The contents of that buffer can be frozen
by selectable conditions, for example when an error occurs.  Thus the
contents can be read out without overwriting saved information.
There is also an option to suppress tracing of
PU-Sense/Control-commands to use the complete buffer for
I/O-operations.  If commands arrive simultaneously from both the I/O
and interfering PU-S/C, one of those commands is delayed for one
cycle to record both operations.  This way of recording a dedicated
number of I/O-operations allows identification of the operations that
were done last and of those that have not yet finished.

      In the chosen embodiment, four busses were provided with each
bus having up to 8 Bus-Units.

      The four arbiters are located in bo...