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Scalable Coherent Interface Clock Generation Alternatives

IP.com Disclosure Number: IPCOM000106492D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21

Publishing Venue

IBM

Related People

Burton, RW: AUTHOR [+6]

Abstract

Two alternatives for generating clocks for use in Scalable Coherent Interface (SCI) logic are discussed. The first alternative performs dynamic phase adjustment to maintain synchronous clocks for the interface logic and the SCI net. The second alternative introduces a shift register data-flow to maintain the synchronous clocks in the interface logic and SCI net.

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Scalable Coherent Interface Clock Generation Alternatives

      Two alternatives for generating clocks for use in Scalable
Coherent Interface (SCI) logic are discussed.  The first alternative
performs dynamic phase adjustment to maintain synchronous clocks for
the interface logic and the SCI net.  The second alternative
introduces a shift register data-flow to maintain the synchronous
clocks in the interface logic and SCI net.

      The IEEE Scalable Coherent Interface (SCI) consists of 16 bits
of data plus flag and clock bits.  A SCI node contains an incoming
and outgoing port.  These ports may be cabled together as a ring as
shown in Fig. 1.  The SCI ring operates at frequencies in the range
of 500MHz.  Each cycle the output ports will produce a unit of
information called a symbol.  The symbols are classified as either
IDLE or non-IDLE symbols.  The non-IDLE symbols are grouped together
into packets.  The number of (non-IDLE) symbols in a packet is always
evenly divisible by 4.  Packets are used for all transfer of
commands, messages, and data on the SCI.  The IDLE symbols are used
to provide part of the flow control information for the SCI and to
maintain synchronization between units.  The flow control information
effects when a node can introduce new packets on the SCI.  IDLE
symbols are also used to fill the gaps between packets.  In any case,
the IDLE packets do not pass any data or control information
resulting in work for the logic interfacing to the SCI port.  When a
packet is passed out an output port, one or more IDLE symbols are
required to be placed on the ring before the next packet is started.
So in the case the output port has two packets to send, an IDLE
symbol will be placed on the SCI ring between the packets.

      The SCI in/out ports are built out of two components, the
Transport component which contains the logic interfacing directly
with the SCI network, and the application component containing which
operates at the slower clock rate IE 1/4th the SCI clock rate.  The
dataflow and clock relationships for the Transport/Application
interface are shown in Fig. 2.  The clock relationships used on the
interface is shown in Fig. 3.  When packet transfers are in progress
4 symbols are passed across the interface each application clock
cycle.  The IDLEs on the SCI are not observed at the
Transport/Application interface, rather the IDLE symbols are
processed within the Transport component.

      The high frequency of the SCI net is desirable from a
performance standpoint, but logic operating at those frequencies will
consume a considerable amount of power.  Implementing a design using
SCI clock rates throughout the SCI logic would be extremely
difficult.  To reduce the power consumption to a manageable level,
and ease the design effort, the majority of the logic in the SCI
interface chips will operate at a lower frequency.  This is
accomplished by widening the internal dataflow by the s...