Browse Prior Art Database

Multiple DMA Channel Hardware Queuing

IP.com Disclosure Number: IPCOM000106499D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 116K

Publishing Venue

IBM

Related People

Becker, DE: AUTHOR [+5]

Abstract

A solution to throughput problems on a multiple DMA channel controller which needs to execute sequential operations to one device is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multiple DMA Channel Hardware Queuing

      A solution to throughput problems on a multiple DMA channel
controller which needs to execute sequential operations to one device
is disclosed.

      A multiple DMA channel controller is capable of having
microcode setup and start multiple operations to transfer data to or
from the same device.  Having multiple channels allows overlap of
setup and execution of operations.  The controller then completes the
outstanding operations without regard to sequence.  If operations
need to occur sequentially, the ability to overlap setup and
execution is lost and effective throughput is less.  Multiple DMA
channel hardware queuing provides a mechanism to achieve overlapped
setup and execution when operations need to be sequenced.

      A queuing mechanism implemented in hardware allows microcode to
setup and start a DMA operation and while this operation is
executing, set up follow-on operations on other DMA channels which
are queued to start once the previous operation has completed.  This
improves throughput of the controller because there is no microcode
intervention required to start the next sequenced operation as
hardware handles that as soon as the prior operation completes.

      A hardware queuing mechanism can improve multiple DMA channel
controller throughput for multiple operations that need to happen
sequentially because operation setup and execution can be overlapped.
Microcode sets up an operation, starts it and goes on to setup
subsequent operations.  Meanwhile, hardware has started execution of
the first operation and as that operation completes, hardware can
start execution of the next queued operation without microcode
intervention which takes significantly more time.  Microcode
intervention would require receiving notification that the first
operation had completed via an interrupt, halting setup of new work
to service the interrupt and then starting the second operation.
Hardware queuing eliminates the need for microcode intervention,
thereby improving throughput in the controller.

The characteristics of this hardware queuing function are:

o   When queuing is activated for a channel, hardware automatically
    determines whether the operation on that channel can begin or if
    it needs to wait for the previous operation to end.  Once the
    prior operation has completed, hardware starts the new operation
    without microcode intervention.  A Queued Status Indicator bit is
    provided indicating that the channel is queued and awaiting
    execution.

o   Flexibility in that any channel can be queued to start after any
    other cha...