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Passing Data Stream Across Asynchronous Clock Domains in Scalable Coherent Interface Bus

IP.com Disclosure Number: IPCOM000106508D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 100K

Publishing Venue

IBM

Related People

Fuhs, RE: AUTHOR [+3]

Abstract

Since clock domain B is asynchronous to clock domain A it is necessary to double latch the Valid Bits in clock domain B to prevent metastability problems in clock domain B. To do this double latching of the Valid Bits with a reduced number of latches a Sliding Window Synchronizer was used. The Sliding Window Synchronizer is made up of three parts, the window selector (W) , some small number of synchronizing latches (S) (4 pairs in this case), and the bit selector (B) .

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This is the abbreviated version, containing approximately 52% of the total text.

Passing Data Stream Across Asynchronous Clock Domains in Scalable Coherent Interface Bus

      Since clock domain B is asynchronous to clock domain A it is
necessary to double latch the Valid Bits in clock domain B to prevent
metastability problems in clock domain B.  To do this double latching
of the Valid Bits with a reduced number of latches a Sliding Window
Synchronizer was used.  The Sliding Window Synchronizer is made up of
three parts, the window selector (W) , some small number of
synchronizing latches (S) (4 pairs in this case), and the bit
selector (B) .

      The window selector is a multiplexor that selects n Valid Bits
(4 in this case) from the array Valid Bits and gates them into the
synchronizing latches.  The window selector has all the Valid Bits as
inputs and has n outputs (4 in this case).  The first output of the
window selector can select between Valid Bits 0, n, 2n, 3n, etc.  The
second window selector output can select between Valid Bits 1, 1+n,
1+2n, 1+3n, etc. This sequence continues for each window selector
output.  In other words each output of the selector can select
between every n'th Valid Bit.  The operation of the window selector
and bit selector is controlled by the logic reading the array in
clock domain B.  After every increment of the array reading address
one output of the window selector 'advances' by n bit positions.
This allows each Valid Bit to be selected to drive a pair of
synchronizing latches for n cycles.

      As a Valid Bit is selected by the window select...