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Error Correction Circuit with Fast Pass through in Parity Mode

IP.com Disclosure Number: IPCOM000106509D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Aldereguia, A: AUTHOR [+5]

Abstract

Disclosed is a circuit which can function to provide either error correction or simple parity checking. For a parity mode function, a shunt is provided to allow the data path to bypass the ECC (Error Correcting Code) decode and correction logic, thereby significantly reducing the time required for propagation through the logic.

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Error Correction Circuit with

Fast

Pass

through in Parity Mode

      Disclosed is a circuit which can function to provide either
error correction or simple parity checking.  For a parity mode
function, a shunt is provided to allow the data path to bypass the
ECC (Error Correcting Code) decode and correction logic, thereby
significantly reducing the time required for propagation through the
logic.

      As shown in the Figure, the data path from system memory
through receiver 10 is provided with a shunt 12, which is activated
in the parity mode.  In the error correction mode, shunt 12 is not
activated, so data from memory must flow through decode and
correction logic 14 and driver 16.

      Shunt 12 can be implemented simply as a transistor.  This
circuit has an advantage of eliminating unnecessary signal delay,
when compared to an alternative of providing a multiplexor at the
input of driver 16, to choose between the output of receiver 10 in
parity mode and the output of logic 14 in error correction mode.
This circuit further has an advantage of requiring much less
additional silicon than the alternative of providing an additional
driver (per bit) so that both the outputs of receiver 10 and of logic
14 can be provided as inputs to separate drivers dotted together.