Browse Prior Art Database

32-Bit Free Running Diagnostic Timer

IP.com Disclosure Number: IPCOM000106514D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 193K

Publishing Venue

IBM

Related People

Noll, MG: AUTHOR

Abstract

Disclosed is a 32-bit free running timer circuit, which cannot be accessed, or loaded, during normal operation. The timer counts from 00000000 up to FFFFFFFF, as expressed in hexadecimal numbers, and then wraps back to 00000000 to start again. While this circuit gives any programmer, writing an application program for the system in which the timer circuit is employed, access to an independent time base, no programmer has the capability of using the circuit exclusively for his application.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 33% of the total text.

32-Bit Free Running Diagnostic Timer

      Disclosed is a 32-bit free running timer circuit, which cannot
be accessed, or loaded, during normal operation.  The timer counts
from 00000000 up to FFFFFFFF, as expressed in hexadecimal numbers,
and then wraps back to 00000000 to start again.  While this circuit
gives any programmer, writing an application program for the system
in which the timer circuit is employed, access to an independent time
base, no programmer has the capability of using the circuit
exclusively for his application.

      As shown in Fig. 1, a 32-bit timer includes eight 4-bit
counters 10, each of which counts pulses arriving at a CLK input.
The first stage of these counters counts pulses supplied by the TIMER
CLK signal, while the other counters are tied together in series, so
that each stage counts the completion of the counting process in the
preceding stage.  Each counter 10 can also be loaded with a digital
code provided by three input lines, P0 through P3, when a load signal
is placed on the LD input line.  Each counter 10 can also be reset to
an "all zeros" count by the application of a reset signal to an RST
line.  Each counter 10 also provides four outputs, Q0 through Q3,
from which the level of the count within the counter can be read.

      The counter circuit of Fig. 1 also includes four 8-bit
registers 12, each of which includes eight input lines, B0 through
B7, and eight corresponding output lines, Q0 through Q7.  The inputs
of each register 12 are tied to the outputs of two adjacent stages
from counters 10.  The values of these inputs are latched into the
register when a signal is presented at the CLK input of the register.
A signal, DIAG_OUT_CLK, is provided for this purpose.  Each register
12 can also be reset to an "all zeros" level by applying a reset
signal to an RST line.  Each register also provides eight outputs, Q0
through Q7, which are directed along output lines 13 to a read
multiplexer (not shown) of the system, where they are read at
addresses 4C through 4F.

      Under appropriate conditions, data can be loaded into the
counters 10 by writing to the associated address, 4C through 4F.
Four load signals, P_LOAD_4C, P_LOAD_4D, P_LOAD_4E, and P_LOAD_4F,
are provided by the system for this purpose.  Data to be loaded is
provided on eight input lines as XDATA(0:7) signals.  For example,
the first two counter stages are written at address 4C by providing
the P_LOAD_4C load signal, so that data from the first four input
signals, XDATA(0:3), is loaded into the first counter stage, while
data from the second four input signals, XDATA(4:7), is loaded into
the second counter stage.

      The timer also includes an 8-bit command register at address
4B, of which latch 14 for Bit 0, latch 16 for Bit 1, and latch 18 for
Bit 5 are shown in Fig. 2.  Each of these latches is of a type which
is set to a zero or one level by a data input D, when a clock input
signal on line B follo...