Browse Prior Art Database

Interlevel Metal Conductor

IP.com Disclosure Number: IPCOM000106521D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 82K

Publishing Venue

IBM

Related People

Gut, GM: AUTHOR [+3]

Abstract

As semiconductor chip integration levels increase the delay contribution from metal wires within the chip tends to increase while the delay from the transistors themselves is being reduced significantly. This leads to a situation where the wiring delays approach the delay of the logical circuit itself. Back end of line (BEOL) wiring capacitance has become a principle system performance limiter with shrinking physical geometries and larger chip sizes. System performance is often limited by a relatively small number of circuit paths (i.e., the longest paths) and these paths typically have the longest metal wire lengths. Capacitive delays in these long wires often make up 30-40% of the total delay.

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Interlevel Metal Conductor

      As semiconductor chip integration levels increase the delay
contribution from metal wires within the chip tends to increase while
the delay from the transistors themselves is being reduced
significantly.  This leads to a situation where the wiring delays
approach the delay of the logical circuit itself.  Back end of line
(BEOL) wiring capacitance has become a principle system performance
limiter with shrinking physical geometries and larger chip sizes.
System performance is often limited by a relatively small number of
circuit paths (i.e., the longest paths) and these paths typically
have the longest metal wire lengths.  Capacitive delays in these long
wires often make up 30-40% of the total delay.  This technique will
allow the metal to metal line capacitance of selected critical paths
to be reduced, thus improving the achievable system speed.  By moving
selected lines to another vertical wiring plane, the parasitic
capacitance between critical path wires and adjacent wires can be
reduced without adding significant process complexity.

      Fig. 1 shows a typical cross-section of a metal wiring level
(level M) with nominal relative dimensions as indicated.  Recent
advanced in semiconductor processing have tended to decrease the
values of "y" and "z" (the horizontal line- width and spacing between
metal wires) but the value of "x" (the vertical height of metal
wires) has remained relatively fixed due to wire current carrying
requirements.  By moving the center of the 3 level M wires to another
vertical plane the inter-wire capacitance can be reduced
significantly.  Notice that up to one half of the wires in level M
could b...