Browse Prior Art Database

Novel Gate Process for 0.1 Micron MOSFETs

IP.com Disclosure Number: IPCOM000106529D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 119K

Publishing Venue

IBM

Related People

Acovic, A: AUTHOR [+4]

Abstract

Disclosed is a gate process suitable for manufacturing sub-quarter micron MOSFETs with good channel doping control by using a removable nitride gate plug on a thin poly-Si gate with oxide refilling and planarization to obtain a self-aligned channel implant after source/drain formation and thus avoid channel doping redistribution during source/drain implant annealing.

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Novel Gate Process for 0.1 Micron MOSFETs

      Disclosed is a gate process suitable for manufacturing
sub-quarter micron MOSFETs with good channel doping control by using
a removable nitride gate plug on a thin poly-Si gate with oxide
refilling and planarization to obtain a self-aligned channel implant
after source/drain formation and thus avoid channel doping
redistribution during source/drain implant annealing.

      Control of short channel effect has become a major challenge in
CMOS scaling.  Experimental data have always shown much more severe
short channel effect than that predicted by simulation for devices
with sub-quarter micron channel length.  It is believed that the
out-diffusion of channel doping into the heavily implant-damaged
source/drain (S/D) region during annealing significantly reduces the
effective channel doping, and thus causes the observed strong short
channel effect.

      To solve the aforementioned problem, a novel gate process
(Figs. 1-3) suitable for manufacturing sub-quarter micron MOSFET's is
invented.  In this process, a poly-Si/nitride gate stack is patterned
to form a removable nitride gate plug on a thin poly-Si gate for
self-aligned S/D implant (Fig. 1), and then with oxide refilling and
planarization the nitride gate plug can be removed to open a channel
implant window (Fig. 2).  Threshold voltage and punch-through control
doping can then be implanted through this window and again
self-aligned to the gate.

      Since the S/D doping is implanted first in this process,
implant damage can be annealed out easily before channel implant so
that any loss of channel doping to the S/D region can be avoided.
Compared with an alternative approach having channel doping implanted
through a conventional thick poly-Si gate after S/D formation, the
disclosed process could achieve a much better control of the channel
doping profile.  The self-aligned punch-through control doping in
this process also reduces S/D parasitic capacitance.  The disclosed
process also provides a self-aligned T-gate structure (Fig. 3) with
low gate resistance and low overlap capacitance.  This enable the use
of a Salicide gate process instead of a more difficult Polycide gate
process for 0.1 um MOSFETs.  In addition, contact metal can be landed
directly on the T-gate to further reduce gate resistance...