Browse Prior Art Database

Multi-Purpose, High Performance, Cyclic Redundance Code Error Detection System

IP.com Disclosure Number: IPCOM000106535D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Chapman, RJ: AUTHOR [+3]

Abstract

Data or programs that are loaded from one processor (environment) to another can be verified via a high-speed, hardware Cyclic Redundancy Code (CRC) that resides on both sides of the interface. If the target processor's databus and memory structure are properly accommodated in the CRC design, the CRC hardware can be reused for a number of critical processor tasks:

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multi-Purpose, High Performance, Cyclic Redundance Code Error Detection System

      Data or programs that are loaded from one processor
(environment) to another can be verified via a high-speed, hardware
Cyclic Redundancy Code (CRC) that resides on both sides of the
interface.  If the target processor's databus and memory structure
are properly accommodated in the CRC design, the CRC hardware can be
reused for a number of critical processor tasks:

o   The above mentioned verification of data or program loads from an
    outside environment.

o   Memory fault testing at Power-on-Reset (POR), prior to any
    Initial Program Load (IPL) and during any maintenance actions.

o   Periodic (background or scheduled) recertification of any memory
    resident programs (when the resident programs have embedded CRC
    values at well designed points in the code stream), the memory
    addressing circuits and special purpose circuits (such as the
    Error Correction Code (ECC) decoder circuit).

The basic block diagram of such a circuit is illustrated in Fig. 1.

      For wide data buses, i.e., 32 bits or more, the CRC circuit can
be designed to operate at the bus data rate by employing a bus wide
CRC value based upon the Galois Field matched to the bus width.

      To periodically check the resident program (memory) and the
memory addressing circuits, read preprogrammed segments of the
resident program and pass through the CRC decoder.  Memory bit faults
and most addressing circuit failures will be detected by the CRC
decoder.  For those memory organizations that have wide buses with
the complete ECC encoded word (all data bits plus all ECC bits) on
the bus at the same instant, the ECC decoder can also...