Browse Prior Art Database

Asynchronous Dual Microprocessor Communication Via Bit Flags

IP.com Disclosure Number: IPCOM000106554D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 126K

Publishing Venue

IBM

Related People

Porter, MS: AUTHOR [+3]

Abstract

This invention enhances microcode performance when communicating between two asynchronous microprocessors. The communication is done via setting a bit flag from one of the microprocessor which cannot be overwritten by the setting of a different bit flag from the other asynchronous microprocessor. Hardware maintains the correct bit flag in each register.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Asynchronous Dual Microprocessor Communication Via Bit Flags

      This invention enhances microcode performance when
communicating between two asynchronous microprocessors.  The
communication is done via setting a bit flag from one of the
microprocessor which cannot be overwritten by the setting of a
different bit flag from the other asynchronous microprocessor.
Hardware maintains the correct bit flag in each register.

      The prior art was implemented with both processors being
asynchronous.  Two issues came up in the actual implementation of
that design with two asynchronous microprocessors.  One was that if
both processors actually wrote the same bit to the same value at the
same time, the bit could potentially be flipped twice.  This is
related to asynchronous design issues.  Another problem was caused
during a check scenario where one set of clocks for one register will
stop, while the other continues to run.  The effect of this event was
for the registers to get out of sync (to have different data in the
registers).  Once the registers are out of sync due to the nature of
the design of flipping the bits, there was no way to get the
registers back in sync.  See Fig. 1 for a layout of the previous
patent filed.

      In the previous patent filed when register A is written by
microprocessor A, it will send a one byte "change value" to register
B.  The change value contains a one in the bit location that has been
changed by the write data.  A zero will indicate that the bit was not
changed when microprocessor A wrote it.  Similarly when
microprocessor B writes register B, a one byte value will be sent to
register A containing a one where a bit location has changed states.
A zero indicates the existing bit value was unchanged.

      A simple example is when Register A and Register B contain
'04'X and microprocessor A writes '8C'X.  The "Exclusive Or" of the
old value of register A and the new value being written to register A
will be '88'X.  This value will be sent to register B which will be
"Exclusive Ored" with register B's old value, '04'X generating '8C'X
to be loaded into register B.  Simultaneously, '88'X will be
"Exclusive Ored" with '04'X to generate '8C'X to be loaded into
register A.

      A more complex situation occurs when both microprocessors write
the registers simultaneously.  Register A and B contain '44'X, and
microprocessor A writes 'C4'X, setting bit zero.  Microprocessor B
writes '40'X thus resetting bit five simultaneously.  The change
value from the register A logic will be '80'X and '04'X from the
register B logic.  The "OR" of the two change values will be '84'X.
After applying the "OR" to the old values of the registers the values
of both register A and B will be 'CO'X.

      A further example will illustrate the logic of the "O Ring" of
the "Exclusive Or" results.  Suppose register A and B both contain
the value '00'X.  Microprocessor A and B both simultaneously...