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Browse Prior Art Database

Displaced Metal Conductor

IP.com Disclosure Number: IPCOM000106579D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 98K

Publishing Venue

IBM

Related People

Gut, GM: AUTHOR [+3]

Abstract

As semiconductor chip integration levels increase the delay contribution from metal wires within the chip tend to increase while the delays from the transistors themselves is being reduced significantly. This leads to a situation where the wiring delays approach the delay of the logical circuit itself. Back end of line (BEOL) wiring capacitance has become a principal system performance limiter with shrinking physical geometries and larger chip sizes. System performance is often limited by a relatively small number of circuit paths (i.e., the longest paths) and these paths typically have the longest metal wire lengths. Capacitive delays in these long wires often make up 30-40% of the total delay.

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This is the abbreviated version, containing approximately 52% of the total text.

Displaced Metal Conductor

      As semiconductor chip integration levels increase the delay
contribution from metal wires within the chip tend to increase while
the delays from the transistors themselves is being reduced
significantly.  This leads to a situation where the wiring delays
approach the delay of the logical circuit itself.  Back end of line
(BEOL) wiring capacitance has become a principal system performance
limiter with shrinking physical geometries and larger chip sizes.
System performance is often limited by a relatively small number of
circuit paths (i.e., the longest paths) and these paths typically
have the longest metal wire lengths.  Capacitive delays in these long
wires often make up 30-40% of the total delay.  By moving selected
lines to another vertical wiring plane, the parasitic capacitance
between critical path wires and adjacent wires can be reduced without
adding significant process complexity.

      Fig. 1 shows a typical cross-section of a metal wiring level
(level M) with nominal relative dimensions as indicated.  Recent
advances in semiconductor processing have tended to decrease the
values of "y" and "z" (the horizontal line- width and spacing between
metal wires) but the value of "x" (the vertical height of metal
wires) has remained relatively fixed due to wire current carrying
requirements.  Small "z" dimensions are becoming a fundamental
performance limiter in semiconductor critical paths.  Once the
critical wiring paths have been determined by traditional timing
analysis one can identify wires that make up a portion of this path
and have connections only to level M+1 (i.e., no connections to level
M-1).  These wires are next removed from the level M design data and
put into a new design level, M'.  The process sequence is as follows:
Normal back end of line processing is used to define and etch vias
used to connect metal level M-1 to level M.  This is shown in Fig. 2.

      The via definition process is followed by...