Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Efficient Collision Resolution in Interprocessor Communication

IP.com Disclosure Number: IPCOM000106585D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR [+3]

Abstract

A method is proposed to preserve the most progressed transfer in the event of message collision on an interprocessor communication from being destroyed. Furthermore, it is proposed to resume automatically the less progressed transmission after the long transfer has been carried out safely and the less progressed has been gracefully aborted after collision detection.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 61% of the total text.

Efficient Collision Resolution in Interprocessor Communication

      A method is proposed to preserve the most progressed transfer
in the event of message collision on an interprocessor communication
from being destroyed.  Furthermore, it is proposed to resume
automatically the less progressed transmission after the long
transfer has been carried out safely and the less progressed has been
gracefully aborted after collision detection.

      In a parallel processing environment information (Fig. 1)
messages are being exchanged between the individual computers.  To
provide high intercommunication bandwidth as well as reduced access
latency N x N crosspoint switches can be utilized.  Such N
input/output switches allow N/2 concurrent communications of N/2
processing unit pairs to take place without blockage.  On the other
hand, for large numbers of N the intercommunication processors have
to be physically separated from such a centralized crosspoint switch
which implies also a logical separation along the information
transmission path.

      For data throughput optimization it is reasonable to
incorporate data buffering in the adapters.  For access latency
optimization it is advisable to facilitate multilevel distributed
arbitration within such an information transmission system.  That
means, a processor adapter A is starting the information transfer as
soon as it receives the local transmission request disregarding
whether the destination adapter B will als...