Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

New Algorithm for Identification of Interconnect Wiring Defects

IP.com Disclosure Number: IPCOM000106587D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 95K

Publishing Venue

IBM

Related People

Chan, JC: AUTHOR [+3]

Abstract

An algorithm is proposed to automate the isolation of interconnect wiring defects on Printed Circuit Board. The proposed technique requires most of the device modules capable of supporting boundary scan operation, as this is the case in the IBM RS/6000* products. The significance of the new technique is the simplicity of operation, and the accuracy of identifying the defect for corrective action. This represents a significant improvement from the current implementation in the IBM RS/6000 products [1].

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

New Algorithm for Identification of Interconnect Wiring Defects

      An algorithm is proposed to automate the isolation of
interconnect wiring defects on Printed Circuit Board.  The proposed
technique requires most of the device modules capable of supporting
boundary scan operation, as this is the case in the IBM RS/6000*
products.  The significance of the new technique is the simplicity of
operation, and the accuracy of identifying the defect for corrective
action.  This represents a significant improvement from the current
implementation in the IBM RS/6000 products [1].

      With the increasing complexity of circuit boards and surface
mount technology, it is becoming ever more difficult to test wiring
interconnects at the printed circuit board level.  Traditionally,
this was done by applying the test vectors to the circuits through an
external tester which is capable of storing the test patterns and the
corresponding correct responses.  Such tester is known to be complex
and expensive.  In addition, the tester requires direct access points
to the nets at the board level.  Many of today's board test
applications prelude this solution.  Conformal coating on boards, or
contact restrictions for examples, may rule out "bed-of-nails"
probing.  In these structures, testability and dense packaging
technology are conflicting requirements.

      To address this problem, the Boundary Scan Test Architecture
was proposed in IEEE Standard 1149.1.  It is a technique that
simplifies the problem of testing and diagnosing wiring interconnect
defects like shorts, opens, and stuck-at pin faults, which account
for the great majority of board level defects.  In the "Boundary Scan
Architecture", a device on a board is equipped with a shift register
that accompanies each I/O pin.  These registers are serially
connected to form a shift-register path around the I/O periphery of
the device.  Through this shift register path, the test system can
control and observe all device pins and associated wiring
interconnects [2].

      A boundary scan test consists of two shift operations.  First,
the test patterns is serially shifted to the test site via the
boundary scan path of the shift registers.  The outputs of these
registers then drive the data onto the interconnect wiring.  The
responses are captured at the inputs of the boundary scan shift
registers on the receiver side.  Next, the response vector is shifted
out for analysis.  Simultaneously, the stimulus for the following
test pattern is shifted into the scan path.  Thus, each test
operation is accomplished through a sequence of serial shifting.  For
each input stimulus applied, there is a corresponding test response
to be captured and stored for analysis.

      The Proposed Algorithm - The fault detection algorithm proposed
in this is disclos...