Browse Prior Art Database

Planar Memory Boundary Registers with Remap Feature

IP.com Disclosure Number: IPCOM000106590D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Stelzer, KC: AUTHOR

Abstract

Disclosed is a method for recovering good memory blocks within the lowest addressable bank of planar (system board) memory, when a memory test finds one or more bad memory locations within this memory bank. A remap address register is used, along with boundary registers, to try to recover the rest of the good memory blocks in the bank. If bad memory locations are found with addresses in the lower half of this bank, the remap feature should be used; if bad memory locations are found with addresses in the upper half of this bank, the boundary registers should be used. When the remap feature is used, the value programmed into the remap register is subsequently used to modify the physical address when planar memory is accessed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Planar Memory Boundary Registers with Remap Feature

      Disclosed is a method for recovering good memory blocks within
the lowest addressable bank of planar (system board) memory, when a
memory test finds one or more bad memory locations within this memory
bank.  A remap address register is used, along with boundary
registers, to try to recover the rest of the good memory blocks in
the bank.  If bad memory locations are found with addresses in the
lower half of this bank, the remap feature should be used; if bad
memory locations are found with addresses in the upper half of this
bank, the boundary registers should be used.  When the remap feature
is used, the value programmed into the remap register is subsequently
used to modify the physical address when planar memory is accessed.

      The Figure provides a block diagram of the Bank 0 address
decode, in which addresses are understood to be binary numbers
corresponding to certain ordered bits in the memory addresses.  The
level of significance of these bits is determined by the size of the
memory being addressed in each block.  Addresses are transmitted
along groups of parallel lines, which are indicated by double lines
in the figure.

      A starting address register 1 holds the starting address for
each bank of planar memory, while the ending address register 2 holds
the ending address range for each bank of planar memory.  The remap
address register 3 holds the value which is added to the cycle
address used to access planar memory, creating a displaced memory
address pointing to good planar memory.

      When a memory cycle occurs, the address is latched in latch 4.
The output of latch 4 is provided as an input to comparator 5, where
the address of the cycle is compared to the starting an...