Browse Prior Art Database

Apparatus to Download and Verify Microcode onto Multiple Processors

IP.com Disclosure Number: IPCOM000106619D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Wu, RH: AUTHOR

Abstract

Disclosed is an apparatus to download multiple pieces of microcode unto a system that consists of multiple processors and multiple pieces of memory. The system consists of n processors (P1, P2,..., Pn) and m pieces of external memory (M1, M2,..., Mm). Some processors share certain memory, but some processors do not have external memory. Each processor has certain amount of internal memory, a vector space and a boot code residing in its Read Only Memory (ROM). There are communication signals among P1 and the rest of processors. On host, one program (Pgm0) starts downloading multiple pieces of microcode (Pgm1, Pgm2, Pgm3) to the target multi_processor system.

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Apparatus to Download and Verify Microcode onto Multiple Processors

      Disclosed is an apparatus to download multiple pieces of
microcode unto a system that consists of multiple processors and
multiple pieces of memory.  The system consists of n processors (P1,
P2,..., Pn) and m pieces of external memory (M1, M2,..., Mm).  Some
processors share certain memory, but some processors do not have
external memory.  Each processor has certain amount of internal
memory, a vector space and a boot code residing in its Read Only
Memory (ROM).  There are communication signals among P1 and the rest
of processors.  On host, one program (Pgm0) starts downloading
multiple pieces of microcode (Pgm1, Pgm2, Pgm3) to the target
multi_processor system.

      Pgm0 downloads Pgm1, Pgm2, Pgm3 to P1's external memory in
sequence.  Pgm1 runs on P1 to control the subsequent downloading.  It
releases a downline processor, sends a signal to that processor, sets
a timer and waits a signal back from that processor.  If the downline
processor has a large external memory, Pgm1 downloads Pgm3 to it and
generates a Cyclic Redundant Code (CRC) to verify.  For processors in
a pipe connection, Pgm1 downloads two pieces of Pgm2 sequentially to
the first processor.  Running on that processor, the first copy of
Pgm2 downloads twice the second copy to the next processor.  This
repeats till the last processor in the pipe and each download is
verified.