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Implementing a CSR-PCS as Multiple Threads

IP.com Disclosure Number: IPCOM000106627D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 6 page(s) / 292K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+2]

Abstract

Multisequencing in a Single Instruction Stream (MSIS) is a uniprocessor organization in which a set of Processing Elements (PE) working in concert execute Segments of the instruction stream in parallel with each other utilizing THREADS that are created during the first pass through the execution sequence. These THREADS monitor the use of registers within the architecture of the instruction set and determine the proper way of maintaining the set/use of register values as well as generating the correct machine state when a SEGMENT completes or is disrupted by a Branch Wrong Guess (BWG). In MSIS-PCS the format of the instruction specifies the instructions that it depends on. Thus there is no need for registers to act as intermediates at the architecture level and for MSIS to discover the relation one dependency at a time.

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This is the abbreviated version, containing approximately 18% of the total text.

Implementing a CSR-PCS as Multiple Threads

      Multisequencing in a Single Instruction Stream (MSIS) is a
uniprocessor organization in which a set of Processing Elements (PE)
working in concert execute Segments of the instruction stream in
parallel with each other utilizing THREADS that are created during
the first pass through the execution sequence.  These THREADS monitor
the use of registers within the architecture of the instruction set
and determine the proper way of maintaining the set/use of register
values as well as generating the correct machine state when a SEGMENT
completes or is disrupted by a Branch Wrong Guess (BWG).  In MSIS-PCS
the format of the instruction specifies the instructions that it
depends on.  Thus there is no need for registers to act as
intermediates at the architecture level and for MSIS to discover the
relation one dependency at a time.  Further the need to recover the
values of registers vanishes with such instructions.

      The point of PCS is that operations exist between instructions
that are supported by registers within a branch group but all these
operations only harden in the memory hierarchy.  In the absence of
registers the dependencies between separate segments of the
computation are only through memory locations and as such the
recovery from a Branch Wrong Guess is merely the canceling of the
STORE operations that have not yet committed.

      In such a system MSIS can replace storage references with
registers that only exist for the communication between portions of
the code that are part of a common Z-SEGMENT and such registers
create no requirement that they be restored when a BWG has occurred
as their raison d'etre was based on solely on the branch being
guessed correctly.

      ROLE OF REGISTERS IN PCS - PCS does not have a register
oriented architecture so that the role of registers is played by
memory locations.  Such memory locations and the values associated
with them are maintained within the FETCH/STORE TABLES within MSIS
and the information stored by one instruction can be accessed
directly by another instruction from these table entries.  It is only
at the conclusion of a P-SEGMENT or when a level of conditionality
associated with a branch has been certified that the information set
within the FETCH/STORE TABLES is committed (hardened) within the
memory of the processor.  We shall assume that all variable locations
are single assignment so that there is no confusion between different
users of the same data and that all variables that are set must be
modified before they are used.

      CSRs are programs designed to run on different processors and
communicate with each other by SEND/RECEIVE protocols.  In a single
assignment realization of CSRs the requirement for SEND/RECEIVE
protocols can be replaced by a modify/unmodify status of output
variables.  If the CSRs are written in PCS the CSRs can be combined
within a single MSIS processor as MSIS THREA...