Browse Prior Art Database

Enhanced I/O Capability for Silicon on Silicon using Solder Columns

IP.com Disclosure Number: IPCOM000106634D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 89K

Publishing Venue

IBM

Related People

Bickford, HR: AUTHOR [+4]

Abstract

Silicon carriers were developed at IBM to provide low cost multi-chip modules that could be manufactured with high wiring densities to accommodate the needs of current and future systems. Another advantage of the silicon carrier is that the thermal expansion coefficient of the carrier is exactly matched to that of the chips, which reduces fatigue and failure of C4 joints during thermal cycling. This will be of increasing importance for future, high power chip sets with higher levels of dissipated heat.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Enhanced I/O Capability for Silicon on Silicon using Solder Columns

      Silicon carriers were developed at IBM to provide low cost
multi-chip modules that could be manufactured with high wiring
densities to accommodate the needs of current and future systems.
Another advantage of the silicon carrier is that the thermal
expansion coefficient of the carrier is exactly matched to that of
the chips, which reduces fatigue and failure of C4 joints during
thermal cycling.  This will be of increasing importance for future,
high power chip sets with higher levels of dissipated heat.

      The silicon carrier with peripheral flex can be I/O bound in
certain applications.  Currently, TAB is used exclusively for I/O,
which limits I/O attachment to the perimeter of the carrier.  As
larger, more complex chip sets are required, the I/O count will
increase significantly - beyond the capability of TAB.  Bringing in
all of the I/O on the perimeter also presents power distribution
problems.  Power and ground contacts are made at significant
distances from the chips, and this distance may vary from chip to
chip.  This is not a desirable situation.  Bringing in all of the
power at the edge of the carrier also introduces simultaneous
switching noise concerns.  These characteristics of the present
version of the silicon carrier have limited its utility to date.

      It is difficult with silicon to make holes through the silicon
to allow for backside attach of area arrays.  This invention,
however, is to use the area on the top of the carrier that is not
used for chip placement to attach an area array of solder columns.
An area array of solder columns has two major advantages over the use
of TAB.  First, it will generally allow a greater number of I/O than
are possible using TAB, and secondly, the interconnects will surround
the chips (Figure).  The connections closest to the chips can be used
for power and ground co...