Browse Prior Art Database

One-Chip Processors and an Unconditional Branch

IP.com Disclosure Number: IPCOM000106662D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+3]

Abstract

With a single chip design, that chip having both the processor and the cache on the chip, a question arises as to how access to the GPRs by the cache controls can improve processing. Clearly a single chip design affords the opportunity to perform many additional functions within the cache-access path due to the proximity and availability of current copies of the GPRs (general purpose registers). In this disclosure we shall consider only those aspects that relate to the handling of unconditional branches within the cache controls.

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One-Chip Processors and an Unconditional Branch

      With a single chip design, that chip having both the processor
and the cache on the chip, a question arises as to how access to the
GPRs by the cache controls can improve processing.  Clearly a single
chip design affords the opportunity to perform many additional
functions within the cache-access path due to the proximity and
availability of current copies of the GPRs (general purpose
registers).  In this disclosure we shall consider only those aspects
that relate to the handling of unconditional branches within the
cache controls.

      INSTRUCTION SCANNING WITHIN THE CACHE CONTROLS - It is usually
the situation that a cache is far removed from the instruction
processor and the contents of the GPR's need to translate the
information within an instruction to addresses within the system is
absent.  However within a single chip processor the access to the
GPR's by elements of the cache controls is not precluded and in the
case of branch instructions the information within the instruction
can often be translated into targets of I-FETCHING using GPR
information.  To make the matters more clear, let us posit that a
scanning mechanism, exists that can extract from the I-STREAM as
presented by the cache the instruction image of an up-coming branch
and such a branch is an unconditional branch.

      SPECIAL CIRCUMSTANCES FOR AN UNCONDITIONAL BRANCH - It can be
assumed that an unconditional branch is taken and with a proper value
of the register(s) used to develop the address, the target of the
branch can be used to perform the necessary I-FETCHING and the branch
instruction suppressed.  Thus, the ability of the cache controls to
develop the branch target precludes the need for the processor to see
the branch instruction.  The cache controls upon detecting an
uncondition...