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Improved I-Fetching from a Common Cache

IP.com Disclosure Number: IPCOM000106665D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 108K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+3]

Abstract

A cache can be comprised of independent and separately addressable units that can operate in parallel. In fact during the usual form of cache access the arrays of the cache are accessed in parallel to offer the candidates for a "late select." In a cache with a separate ACCESS and CONTENT directory only one of the Set Associativity Units (SAU's) is accessed while the others are free to perform other functions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Improved I-Fetching from a Common Cache

      A cache can be comprised of independent and separately
addressable units that can operate in parallel.  In fact during the
usual form of cache access the arrays of the cache are accessed in
parallel to offer the candidates for a "late select." In a cache with
a separate ACCESS and CONTENT directory only one of the Set
Associativity Units (SAU's) is accessed while the others are free to
perform other functions.

ACCESS DIRECTORY AND CONTENTS DIRECTORY

o   L1-Access Directory - The access Directory is a direct mapped
    directory that converts the access from the processor into a
    position in the cache to allow parallel access and when elements
    of the cache that have different set associativities are
    involved.  The cache supports parallel operations within
    different SAUs.  The size of the L1-Access Directory in cache
    lines can be much larger than of the size of the cache arrays in
    lines.

o   L1-Contents Directory - The Contents Directory is a set
    associative directory that is used to make replacement decisions
    and each entry points to a line that is actually present in the
    cache arrays.  The L1-Contents Directory contains the real
    address tags of the lines in the cache The size of the Contents
    Directory in cache lines is the same as size of the cache arrays
    in lines.

In the case of a LOAD access to the L1-CACHE, bits are selected from
the virtual address, VCC sub ACCESS , to access the L1-Access
Directory.  The number of bits within the VCC sub ACCESS  is directly
related to the size of the L1-Access Directory as the L1-ACCESS
DIRECTORY is direct-mapped.

      The parallelism between  SAUs is restricted by the limitation
that the ACCESS and CONTENTS directories have only a single port so
that only one access from the processor can be handled in a given
cycle.

      APPLICATION TO I-FETCHING - The information within the ACCESS
directory specifies the location within the CONTENTS directory of the
real address tag of the line by indicating both the congruence class
and the set associativity position within that congruence class.
Thus only that information need be accessed from the CONTENTS
directory to verify that the correct line is being accessed.  This
verification is based on comparing the real address tag within the
cache directory and the output from the DLAT (TLB -Translation
Lookaside Buffer).  The information within the access directory also
specifies the location within the arrays of the cache of the
"zero-th" doubleword (DW) of the line being accesses.  We shall
assume that the unit of access from the cache is a doubleword (DW)
but this assumption is not essential to the efficacy of what is being
disclosed.

      LATIN SQUARE LAYOUT - A cache line is comprised of 128 Bytes,
say, on a 128 B boundary.  This comprises 16 DWs.  These DWs can be
placed in the arrays of the cac...