Browse Prior Art Database

Automatic Voter Test Circuit

IP.com Disclosure Number: IPCOM000106667D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Tremaine, RB: AUTHOR

Abstract

Disclosed is a mechanism to "transparently" test voter circuits within fault tolerant synchronous interfaces. A hardware circuit senses and "steals" idle traffic cycle(s) through a voter, during which predetermined test patterns are processed through the voter. This mechanism enables periodic verification of voter integrity without software intervention or degradation to interface throughput. The Voter Test Circuit (VTC) is implemented in hardware together with a voter-checker, as shown in Fig. 1. The parts of the design that are particular to the test circuit are shown with solid lines.

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Automatic Voter Test Circuit

      Disclosed is a mechanism to "transparently" test voter circuits
within fault tolerant synchronous interfaces.  A hardware circuit
senses and "steals" idle traffic cycle(s) through a voter, during
which predetermined test patterns are processed through the voter.
This mechanism enables periodic verification of voter integrity
without software intervention or degradation to interface throughput.
The Voter Test Circuit (VTC) is implemented in hardware together with
a voter-checker, as shown in Fig. 1.  The parts of the design that
are particular to the test circuit are shown with solid lines.

Theory of Operation - The The VTC operates on the basis that the
voter-checker is a combinatorial circuit within a synchronous system.
Within this environment, an information symbol is passed through the
voter-checker every system clock cycle.  Each cycle can be classified
as data, control or idle by attributes from the data symbol.  When
the VTC detects an idle cycle, it preempts the data flow into the
voter-checker with test data stored or generated locally in hardware.
The voter-checker output and status will be regenerated with respect
to the test arguments.  Since the test will have corrupted the idle
symbol, a multiplexor is provided in the data flow to the rest of the
system to reproduce the "stolen" idle symbol to the rest of the
system.  The cycle timing diagram, shown in Fig. 2, reflects how the
test progresses through time.

      No additional hardware is required to process/handle the test
results from the voter-checker.  Voter status during test cycles is
handled normally together with a status indication that the...