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Realizing an L2 as an Extension of an L1

IP.com Disclosure Number: IPCOM000106672D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+2]

Abstract

As lines from MRU to LRU within the L1 cache, there is no movement of the line. Rather the ordering of the line is done with respect to age-tag indicators. When the line ages beyond the size of the L1 cache then the line is replaced and lost from the L1 cache. One can design a second level in the cache hierarchy that is loaded on parallel with the L1 and is larger. This level called an L2 contains all the lines that have been aged out of the L1 cache and not yet out of the L2 cache as the larger. If the L2 geometry is the same as the L1 geometry and information about MRU changes are propogated from the L1 cache to the L2 cache the age-tags within both caches keep identical records as to the status of all lines within a congruence class.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Realizing an L2 as an Extension of an L1

      As lines from MRU to LRU within the L1 cache, there is no
movement of the line.  Rather the ordering of the line is done with
respect to age-tag indicators.  When the line ages beyond the size of
the L1 cache then the line is replaced and lost from the L1 cache.
One can design a second level in the cache hierarchy that is loaded
on parallel with the L1 and is larger.  This level called an L2
contains all the lines that have been aged out of the L1 cache and
not yet out of the L2 cache as the larger.  If the L2 geometry is the
same as the L1 geometry and information about MRU changes are
propogated from the L1 cache to the L2 cache the age-tags within both
caches keep identical records as to the status of all lines within a
congruence class.  The loading of lines is done from the memory (L3)
in the case of a miss from the L1 that is not found in the L2 and
from the L2 in the case of an L1 miss that is found in the L2.  The
line replaced in the L1 is already a part of the L2 in such a
situation and in the case of an L2 "hit" all that is required is to
reassign the age-tag indicators of the lines interchanged by the L2.

BUSES AND HOW THEY ARE USED - There are two buses in the system of
concern:

o   the bus between the L2 cache and the L1 cache, B21, and

o   the bus between the L3 memory, B31, and the caches.

The bus between the L2 and the L1 cache is used during an L1 cache
miss that is found in the L2.  In support of a WI (Write In) L1 level
the bus is also used to handle a cast-out of modified lines to the L2
where they must further be cast-out to the memory.

      The bus between the memory and both caches is used during a
miss from the L1 that is not found in the L2.  A line is presented to
both caches in parallel in the usual configuration.

REALIZING AN L2 AS AN EXTENSION ON AN L1 - To maintain the L1 and L2
with non-overlapping sets of lines on an overall basis, it is
sufficient that the activity on each L1 cache miss and assure the
non-overlap by doing the following:

o   The loading of a line is done directly from the memory into the
    L1, if the line accessed is neither in the L1 nor the L2.  Such a
    line uses the B31 to load a line from the memory and allows the
    B21 to be used to pass the line that is being replaced into the
    L2.  The longer access time of the L...