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Scanning, Scheduling and Prioritizing within a Three-Stream Machine

IP.com Disclosure Number: IPCOM000106673D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+3]

Abstract

A single chip processor affords an access to the GPRs from all parts of the chip and it becomes possible to implement a branch co-processor within the cache controls so as to improve performance. The operations of the three stream machine are outlined in [*], and our concern here is to detail the scanning, scheduling, and prioritization issues that arise in the context of a single port common cache.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Scanning, Scheduling and Prioritizing within a Three-Stream Machine

      A single chip processor affords an access to the GPRs from all
parts of the chip and it becomes possible to implement a branch
co-processor within the cache controls so as to improve performance.
The operations of the three stream machine are outlined in [*], and
our concern here is to detail the scanning, scheduling, and
prioritization issues that arise in the context of a single port
common cache.

      Because the branch co-processor is part of the cache controls
it is assumed that the cache access for the branch co-processor is a
single cycle while the cache access of the main processor is two
cycles.  The function of the scan processor, the third machine in the
three stream machine is to identify which processor is to execute
which instructions within the instruction stream.  The candidate
instructions for the branch co-processor are unconditional branches,
conditional branches, Test under Mask (TM), Compare Logical Immediate
(CLI), and Load (L) instructions that cause address generate
interlocks with respect to these and the other instructions presented
to the main processor.  The main processor execute instructions via
micro-code controlled execution that alter the state of the system by
changing the contents of General Purpose Registers (GPRs) or memory
locations.

HOW DOES THE MACHINE START UP? - As the processor must anticipate the
action of some branches prior to their resolution especially in the
case where the condition code (CC) is set by a multicycle microcode
controlled instruction execution it would seem that the process of
co-execution, scanning, and and scheduling can begin following a
branch wrong guess.

      The prime objective is to execute as many instruction without a
delay while maintaining concurrency of execution.  As the cache port
is a single resource shared by both processors, attention must be
paid to the number of outstanding non-branch register/register
instruction (RR-ops) that exist in the main processor stream.  Such
instructions afford the opportunity to execute instructions from both
streams concurrently.  At the same time, one wants to resolve the
next upcoming branch so that the next branch group can be processed
without...