Browse Prior Art Database

Universal Clock Generator

IP.com Disclosure Number: IPCOM000106674D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 102K

Publishing Venue

IBM

Related People

Bredin, F: AUTHOR [+2]

Abstract

This circuit is intended for use in RAM or ROS systems where feedback servitude scheme is employed. Potential applications are numerous, for example, AC checking of any growable array in mode self test, automatic adjust of the clock generator in case of process, temperature and/or voltage variations.

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This is the abbreviated version, containing approximately 52% of the total text.

Universal Clock Generator

      This circuit is intended for use in RAM or ROS systems where
feedback servitude scheme is employed.  Potential applications are
numerous, for example, AC checking of any growable array in mode self
test, automatic adjust of the clock generator in case of process,
temperature and/or voltage variations.

      Two operating modes are provided: the normal mode and the
circuit produces some pulses to command, synchronize and control the
different parts of the memory and the self test mode to work together
with an external address generator and a data output checker.

      As shown in Fig. 1, the basic UCG scheme is constituted by a
gating logical block (OR6) where is applied the Normal/Test (N/T)
input and the Ros Clock (RC).  The RC input signal must be low and
N/T high to allow the relaxation mode.  A holding latch (HOLD "H"),
it maintains the B node to high level till MS or Y switch to low
level and reset the latch through N2 device.  A wordline decoder
which is gated by the generated pulse (P).  A selected wordline WL
coming from the wordline decoder where is connected an equivalent
capacitance (CB) which represents the sum of the bitlines.  The dummy
bitline (DBL) which is selected by any wordline (e.g., WL) and where
is connected an equivalent bitline capacitance (CW) which represent
the field of the wordlines (CW).  A feedback block which gives the
FEDB pusle.  The FEDB pulse is a transitive pulse.  It is
respectively set and reset by the sensing of the dummy bitline
variation (DBL) and the FEDB falling transition pulse itself going
through NAND4 (node S).  A logic loop, which consist in AND2, NOR3
and INV5.  The rising pulse generates a negative pulse through INV5,
which is applied to AND2 and maintain a low logical level at the node
A and by this way inhibits the path coming from NAND1.  NOR3 will be
reset by the FEDB low transition pulse.  N1 and N3 NMOS device which
are intended for the reset and  the triggering of the UCG system in
relaxation mode.  P pulse follows B pulse.  B pulse is calibrated by
the duty...