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Apparatus for Multi-Processor Direct Memory Access Operations and Verification

IP.com Disclosure Number: IPCOM000106677D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Wu, RH: AUTHOR

Abstract

Disclosed is an apparatus to conduct and verify multi-processor Direct Memory Access (DMA) operations in a system that consists of six processors (P1, P2, ..., P6) and four pieces of external memory (M1, M2, M3, M4). Each processor has an internal memory and a set of DMA registers. There is a set of signal lines between P1 and each of the rest processors.

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This is the abbreviated version, containing approximately 100% of the total text.

Apparatus for Multi-Processor Direct Memory Access Operations and Verification

      Disclosed is an apparatus to conduct and verify multi-processor
Direct Memory Access (DMA) operations in a system that consists of
six processors (P1, P2, ..., P6) and four pieces of external memory
(M1, M2, M3, M4).  Each processor has an internal memory and a set of
DMA registers.  There is a set of signal lines between P1 and each of
the rest processors.

      In each of the internal memory, two fix-sized buffers called
Source Buffer (SB) and Destination Buffer (DB) are set-up.  P1 sets a
loop count so that the size of SB or DB times the loop count equals
the size of its external memory.  P1 generates an increating data
pattern and puts the data into SB then starts a DMA out to P2.  P2
generates an incrementing pattern and puts the data into its SB, then
P2 does a DMA in from P1 and puts the data into its DB.  P2 compares
data in both SB and DB.  If the data match, P2 signals P1 for
success.  If there is an error, P2 does not signal P1 and P1 times
out.  This process repeats until the number of DMA operations equals
the size of P1's external memory.

      P1 synchronizes the overall operations among the processors.
The multi-processor DMA operations conduct from P1 through the rest
processors to P6.  Each byte of the DMA operation is verified between
each pair of processors.  Data may be transfered from P6 back to P1
through DMA if required.