Browse Prior Art Database

Apparatus to Conduct and Verify Multi-Processor Programmed Input Output Operations

IP.com Disclosure Number: IPCOM000106680D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Wu, RH: AUTHOR

Abstract

Disclosed is an apparatus to conduct and verify the inter-processor Programmed Input Output (PIO) read and write operations among multiple processors in a complex system. The system consists of six processors (P1, P2, P3, P4, P5, P6) and some external memory shared among the processors. Normally data flow from P1 through P2 - P5 to P6, but data may also flow back to P1 from P6 via a shared memory (M3). P1 assumes responsibility of overall synchronization. It has five signal lines called Attention (Att) going to the rest processors. Rest processors have one signal line called Acknowledge (Ack) going back to P1. Each processor has some internal memory.

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Apparatus to Conduct and Verify Multi-Processor Programmed Input Output Operations

      Disclosed is an apparatus to conduct and verify the
inter-processor Programmed Input Output (PIO) read and write
operations among multiple processors in a complex system.  The system
consists of six processors (P1, P2, P3, P4, P5, P6) and some external
memory shared among the processors.  Normally data flow from P1
through P2 - P5 to P6, but data may also flow back to P1 from P6 via
a shared memory (M3).  P1 assumes responsibility of overall
synchronization.  It has five signal lines called Attention (Att)
going to the rest processors.  Rest processors have one signal line
called Acknowledge (Ack) going back to P1.  Each processor has some
internal memory.

      There are four programs (Pgm1, Pgm2, Pgm3, Pgm4) involved.
Running on P1, Pgm1 outputs Pgm4 onto P6 and Pgm4 waits the Att from
P1.  Pgm1 then outputs Pgm2 onto P2 and Pgm2 waits the Att from P1.
Pgm1 sends Att to Pgm2 and outputs Pgm3 to P2.  Upon receiving Att,
Pgm2 inputs Pgm3 to a designated location in P2's internal memory.
Pgm1 sets a timer then waits the Ack from P2.  Pgm1 flags an error on
P2 if it times out before the Ack comes in.  After inputting Pgm3,
Pgm2 writes P2's signature into a designated location in Pgm3's data
area then sends the Ack and waits for next Att.  On receiving the
next Att, Pgm2 outputs Pgm3 to P3 twice.  Running on P3, the first
Pgm3 inputs the second Pgm3 to a designated loc...