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Selecting the Next Line to Update the L2 from the Store Stack

IP.com Disclosure Number: IPCOM000106690D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Rechtschaffen, R: AUTHOR

Abstract

Given a system of processors operating with WTWAX L1 caches, the need exists to process the stores so that the delay associated with a request for a line is as short as possible. As the line requested can be any line that has been stored into an algorithm for applying stores to the L2 which minimizes the exposure to a random request is sought.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Selecting the Next Line to Update the L2 from the Store Stack

      Given a system of processors operating with WTWAX L1 caches,
the need exists to process the stores so that the delay associated
with a request for a line is as short as possible.  As the line
requested can be any line that has been stored into an algorithm for
applying stores to the L2 which minimizes the exposure to a random
request is sought.

      The memory hierarchy is ostensibly WTWAX L1 caches and each
store is applied to a a store stack that buffers stores between the
L1 cache and the L2.

A WTWAX cache management protocol is defined as:

o   all stores are written through the L1 cache to the L2 (WT),

o   all lines that are stored into by the processors must be
    allocated (WA - WRITE ALLOCATE), and

o   all lines written into must be held exclusively (X).

      It is possible to use the instructions that perform multiple
stores as a way of reducing the contents of the STORE STACK for lines
that are almost totally stored over by a single instruction.  For
instructions like STM (Store Multiple) and MVC (Move Character) that
can over-write an entire line, the TARGET line can be indicated as
WI.  Thus the cache protocol is a hybrid WTWAX/WI and the buffering
of the stores for these indicated WI lines is within the L1 cache as
opposed to the STORE STACK.

      STORES ARE PROCESSED ON A LINE BASIS - One property of holding
the lines that are subject to stores with exclusive status is that
the architecture is not violated if the stores within the store stack
that go to different lines are done out of conceptual sequence.
Thus, the desire to remove a certain number of stores from the store
stack and apply them to the L2 cache level can be done on a line
basis.  That is, all stores in the store stack that target a specific
line can be removed consecutively even though there may have been
intervening store from other processors.

      LINE STATISTICS GATHERED - For each line that is updated by a
store in the store stack, the processor maintains a bit string
associated with t...