Browse Prior Art Database

Graphics Floating Point Engine Timer

IP.com Disclosure Number: IPCOM000106711D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 91K

Publishing Venue

IBM

Related People

Gariazzo, RE: AUTHOR

Abstract

In the implementation of a Central Processor Unit Complex, one of the most prevailing problems is to predict the behavior of the design. Considering the complexity of today designs, this prediction becomes even more critical and almost impossible to do without the help of a tool. The behavior projection is needed to analyze the design for performance, for comparative analysis when considering alternative Central Processor Units, and for design optimization. The problem became even more acute when predicting behavior for larger instruction traces, where the interaction between stages is almost as active as the processing of the instructions.

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Graphics Floating Point Engine Timer

      In the implementation of a Central Processor Unit Complex, one
of the most prevailing problems is to predict the behavior of the
design.  Considering the complexity of today designs, this prediction
becomes even more critical and almost impossible to do without the
help of a tool.  The behavior projection is needed to analyze the
design for performance, for comparative analysis when considering
alternative Central Processor Units, and for design optimization.
The problem became even more acute when predicting behavior for
larger instruction traces, where the interaction between stages is
almost as active as the processing of the instructions.

      The solution contained in this disclosure is a TIMER
representing the graphics floating point engine (GFPE) pipeline.

      TIMERs are software representations of a Central Processor Unit
complex.  Sometime called 'Register Level Simulator', they represent
a hardware system by modelling it at a very low level, with a great
deal of detail.  The simulation is carried out at the register level,
effectively modeling all the registers used to hold and transfer
information.  In consequence, its time unit is a 'cycle' and it is
its minimum time differentiation possible:  events that take less
than one cycle are not modelled nor considered.

      Within the rigidity imposed by this low level representation,
the solution taken considers flexibility to modify the pipeline or
some of its characteristics.  This allowed to do 'what if' studies
and evaluations of hardware changes and improvements.

      The TIMER (or model) implemented represents precisely  the
GFPE.  It includes all the processing (or execution) stages, their
interconnection, the caches, the memory subsystem, and the
synchronization between all the stages and caches.

The GFPE pipeline modelled is described in Fig. 1.

      The GFPE TIMER performs the simulation by processing
instructions for the GFPE taken from a data set.  Since the TIMER
does not deal with register content, or data, the resolution of any
branch, as...