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Browse Prior Art Database

Specialized Processors Staging Parameters

IP.com Disclosure Number: IPCOM000106719D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 190K

Publishing Venue

IBM

Related People

Pomerene, J: AUTHOR [+3]

Abstract

Specialized Processors have a limited function that is represented by a set of I-LINES that reside in its cache. The size of the cache may limit the potential for specialization as each specialized processor has a minimum utilization requirement. A means of increasing the effective cache size while retaining the specialization advantage is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 25% of the total text.

Specialized Processors Staging Parameters

      Specialized Processors have a limited function that is
represented by a set of I-LINES that reside in its cache.  The size
of the cache may limit the potential for specialization as each
specialized processor has a minimum utilization requirement.  A means
of increasing the effective cache size while retaining the
specialization advantage is disclosed.

      For homogeneous workloads of various types it is possible to
identify particular instructions which we shall call ENTRY POINTS
(EP's).  In execution EP's will TRIGGER a PROCESSOR TRANSITION (PT)
to a specialized processor that is dedicated to the code which
follows the EP in the execution sequence.  The rules that determine
EP's derive from their suitability as triggers for a PT and relate to
the pattern of their occurrence and the characteristics of the
instructions that follow such EP's.

      The sequence of instructions that follow an EP must have
specific properties that determine its qualification.  It is these
properties that serve as a FILTER in determining the use of the
BRANCH to this entry point as the PT TRIGGER.

o   The next N instruction executions, ENTRY sub N, that follow the
    each occurrence of the EP should have substantial commonality.

o   The exception to this rule is that EP within ENTRY sub N are
    exempted.

o   The size of what is considered ENTRY sub N is the measured in
    terms of cache lines.  Given an EP and what then qualifies as
    ENTRY sub N, the total number of instructions executed can vary
    by the amount of consecutive executions that stay within these
    cache lines.  Due to variations of branch actions not all cache
    lines need be used for each EP occurrence.

o   Instructions within ENTRY sub N need not be unique and can be
    repeated outside of ENTRY sub N.

o   There can be variations within ENTRY sub N that can be associated
    with different branch action

An illustration of the environments in which specialized processors
can be dynamically created and used to advantage in a homogeneous
workload is given in the following schematic:

     *----------*----------*----------*----------*

     |    S1    |    S2    |    S3    |   S4     |

     *----------*----------*----------*----------*
where S1, S2, ....  are stages of processing of the transaction using
different programs.

      If such transaction processing is done within a uniprocessor,
or done in its entirety within processors of a multiprocessor, the
advantages of isolating the processing of individual stages to
separate processors can not be realized.  If we consider a pipeline
of such transaction processing within a set of dedicated processors,
as shown below, the advantages of isolating a stage to a processor
can be realized.

     *----------*----------*----------*----------*

     |    P1    |    P2    |    ...