Browse Prior Art Database

Reduced Power Delay Line Implementation

IP.com Disclosure Number: IPCOM000106725D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 119K

Publishing Venue

IBM

Related People

Correale Jr, A: AUTHOR [+2]

Abstract

Programmable delay lines are used in a variety of applications requiring a fixed delay which is compensated for power supply, temperature, and processing variations. The delay lines can be used to generate signals with a precise phase relation between themselves. The delay elements used to construct the delay lines are typically designed to optimize their delay matching. In typical delay line implementations, the signals through the delay lines are free running. This can lead to significant power dissipation within the delay lines. This disclosure addresses the design of a delay element which can be powered-off when not selected, leading to lower overall power dissipation.

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Reduced Power Delay Line Implementation

      Programmable delay lines are used in a variety of applications
requiring a fixed delay which is compensated for power supply,
temperature, and processing variations.  The delay lines can be used
to generate signals with a precise phase relation between themselves.
The delay elements used to construct the delay lines are typically
designed to optimize their delay matching.  In typical delay line
implementations, the signals through the delay lines are free
running.  This can lead to significant power dissipation within the
delay lines.  This disclosure addresses the design of a delay element
which can be powered-off when not selected, leading to lower overall
power dissipation.

      A typical implementation of the delay element is shown in Fig.
1.  The delay element consists of two series p-channel devices, Q1
and Q2, connected to two series n-channel devices, Q3 and Q4.
Transistors Q3 and Q2 form an inverter through which the input signal
is propagated with some delay.  Transistors Q1 and Q4 form current
sources whose gates are tied to regulated bias voltages.  By
controlling the bias voltages on the gates of Q1 and Q4, the delay is
controlled through the inverter formed by Q2 and Q3.

      The delay chain is formed by connecting 'n' delay elements in
series.  The outputs of the delay element are connected to a delay
element input and output buffer.  The output buffer is used to
provide a constant loading at the delay element output.  The buffered
output is then fed to a 1 of 'n' selector from which a delayed signal
is selected.  In this implementation, the entire length of the delay
line switches at the frequency of the input to the delay line.  In
addition, the output buffers and the selector inputs also switch at
the input frequency.  The selectors themselves may be comprised of
several stages of circuitry, which is usually the case for large
width selectors made up of multiple smaller input width selectors.
The combination of the delay line, output buffer, and selector
switching results in a large amount of unwanted power dissipation.

      The modified delay element in Fig. 2 can be used to reduce the
power dissipation.  The circuit consists of two series p-channel
devices, Q1 and Q2, and three series n-channel, Q3, Q4, and Q7.  The
devices Q2 and Q3 again form an inverter through which the input
signal is propagated; devices Q1 and Q4 form the current sources by
which the delay through the delay element is determined.  An
additional device Q7 is inserted whose gate is tied to the decode
signal.  The circuit functions as follows:  when the decode signal is
enabled, device Q7 is on and the delay element propagates the input
signal.  If the...