Browse Prior Art Database

Fast Real-Time Data Input and Compress Algorithm

IP.com Disclosure Number: IPCOM000106726D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 104K

Publishing Venue

IBM

Related People

Medalis, ET: AUTHOR

Abstract

A program is disclosed (and schematically illustrated in flow chart form in the Figure) that relates to the scanning of a quantity of bilevel image data into a lesser quantity of computer memory. The scanner interface repeatedly places two bytes (word) of data into an interface register thus overlaying the previous word. There is a fixed amount of time between the arrivals of input words during which processing can occur and thereby avoid data loss.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Fast Real-Time Data Input and Compress Algorithm

      A program is disclosed (and schematically illustrated in flow
chart form in the Figure) that relates to the scanning of a quantity
of bilevel image data into a lesser quantity of computer memory.  The
scanner interface repeatedly places two bytes (word) of data into an
interface register thus overlaying the previous word.  There is a
fixed amount of time between the arrivals of input words during which
processing can occur and thereby avoid data loss.

      The data is compressed as it is received by using a single
algorithm that alternates between data input and data compression
operations and completes those operations on each input word before
the next word arrives.  The structure of the algorithm's execution
paths is used to remember the bit pattern of the previous data word
processed (state) of the algorithm.  The algorithm path taken is set
without having to test the state.  The way the data input and
compression operations are combined and the lack of testing the
compression state are the items that may be unique.

      A simple compression of adjacent "all white" and adjacent "all
black" words is performed after the data is removed from the
interface register.  The following diagram illustrates the program
logic used to accomplish the task.

Legend:

 - IN             =  Input data from interface register

 - OUT-MD         =  Output Mixed Data to memory

 - OUT-BM         =  Output Black Marker to memory

 - OUT-WM         =  Output White Marker to memory

 - OUT-BC         =  Output Black Count to memory

 - OUT-WC         =  Output White Count to memory

 - DATA           =  Test type of current input data

 - B              =  Black

 - M              =  Mixed (black & white)

 - W              =  White

 - WC1            =  Set White Counter = 1

 - BC1            =  Set Black Counter = 1

 - WC+            =  Increment White Counter

 - BC+            =  Increment Black Counter

The following paragraphs follow the flow through all significant
items in the algorithm.

      Beginning at Item 02 the state is assumed to be mixed.  Item 03
inputs a word of data from the interface register (Item 01).  Item 04
decides the type (mixed, black, white) of the current input word.
The state either remains mixed or changes to black or white.

      If the state remains mixed, Item 05 outputs (to memory) the
most recent input word.  Item 03 will execute, again, after Item 05.

      If the state changes to white, Item 06 outputs (to memory) a
word of all white data to mark the beginning of a "white block" of
input data.  A white block of data always consists of a word of white
data followed...