Browse Prior Art Database

Multisequencing in a Single Instruction Stream without D-List/S-List through Register Renaming

IP.com Disclosure Number: IPCOM000106730D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 159K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+3]

Abstract

Within a Multisequencing in a Single Instruction Stream (MSIS) processor instructions are scheduled on multiple independent processor elements and intercommunicate via S-LIST/D-LIST entries that allow each instruction to use the proper value of the register it references. In this way each processor element that handles a set of instructions in their conceptual sequence has a register file that is used by other instructions when there is no S-LIST entry associated with the instruction. In order to recover from the possibility of a Branch Wrong Guess (BWG) instructions are associated with a Level of Conditionality (LC) that, roughly speaking, corresponds to the number of branches encountered since the beginning of the segment.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 35% of the total text.

Multisequencing in a Single Instruction Stream without D-List/S-List through Register Renaming

      Within a Multisequencing in a Single Instruction Stream (MSIS)
processor instructions are scheduled on multiple independent
processor elements and intercommunicate via S-LIST/D-LIST entries
that allow each instruction to use the proper value of the register
it references.  In this way each processor element that handles a set
of instructions in their conceptual sequence has a register file that
is used by other instructions when there is no S-LIST entry
associated with the instruction.  In order to recover from the
possibility of a Branch Wrong Guess (BWG) instructions are associated
with a Level of Conditionality (LC) that, roughly speaking,
corresponds to the number of branches encountered since the beginning
of the segment.  A table called the ZZT maintains the last changes to
registers made at each level of conditionality and can be scanned to
determine the composite result of the register state of the processor
at each LC and at the conclusion of the Z-SEGMENT.

      MSIS is a uniprocessor organization in which a set of
processing elements (PE) working in concert execute Segments of the
instruction stream.  The Segments are either P-Segments, normal
uniprocessor instruction stream portions, that are processed in the
E-MODE of MSIS and produce Z-Segments, or the Z-Segments that are
processed in Z-MODE by MSIS.  The main difference between E-MODE and
Z-MODE is that during E-MODE each PE sees all instructions in the
Segment and executes the ones that are assigned to it, but during
Z-MODE a PE only sees the instructions assigned to it.

      As all PEs see all instructions in E-MODE, each PE can create
the Z-CODE it will require to re-execute the Segment as a Z-Segment,
the Z-CODE being stored in the Z-CACHE, and associated with
instructions in the Z-CODE are S-LISTS and D-LISTS as appropriate.
An S-LIST instructs the PE, in the Z-MODE, that one or more of the
source registers in an instruction assigned to it is set by another
instruction that is executed on another PE, an S-LIST is a receiving
obligation.  The D-LIST instructs the PE in the Z-MODE as to the
names of PEs that require the values of the register(s) that are
being set by an instruction that is assigned to it.  A D-LIST entry
is a sending obligation.

      ZZT - At the conclusion of a Z-SEGMENT or at the point of a
Branch Wrong Guess, the register state of the processor is
distributed among the register files that constitute the results of
THREAD processing.  To determine the machine state a ZZT is employed.
The ZZT is a two dimensional structure which is accessed by both
architected register name and level of conditionality.  The level of
conditionality of an instruction is assigned to instructions during
the E-MODE and corresponds to the number of:  branch instructions,
serializers, and entry points that are not targets of branches within
the Z-COD...