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Small L2 Options Exclusive Lines

IP.com Disclosure Number: IPCOM000106733D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Ignatowski, M: AUTHOR [+3]

Abstract

Consider a memory hierarchy for a multiprocessing system in which eight processors each having a 128K cache are supported by a single L2 whose capacity is 1 MB. Assume that the individual processors are WI and so for lines held exclusive and modified the only valid copy of the line exists in the L1. The requirement that the L2 contents be a superset over the L1 contents in such a configuration leaves the L2 with very little that is not present in one of the L1 and a better approach ins such a limited L2 configuration is to provide for a greater flexibility in having information in the L1 that is not within the L2.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Small L2 Options Exclusive Lines

      Consider a memory hierarchy for a multiprocessing system in
which eight processors each having a 128K cache are supported by a
single L2 whose capacity is 1 MB.  Assume that the individual
processors are WI and so for lines held exclusive and modified the
only valid copy of the line exists in the L1.  The requirement that
the L2 contents be a superset over the L1 contents in such a
configuration leaves the L2 with very little that is not present in
one of the L1 and a better approach ins such a limited L2
configuration is to provide for a greater flexibility in having
information in the L1 that is not within the L2.

      In a WI cache approximately one fourth of the lines are
modified and these lines must be held exclusive at the point when
they are modified so as to provide for cache coherency within the
system.  The other copies of such  a modified line that are present
in the rest of the system are invalid and as such retention of the
space that these invalid lines occupy wastes space within the cache
directories and arrays.  It would seem that lines that are taken
exclusive by any L1 cache can be invalidated by the L2 and the
directory space and array space that these lines occupy within the L2
be made available for lines that are not within the L1 caches.

      The fate of such modified lines is that they will be accessed
by another processor within the configuration or the space that they
occupy will be required by more recently used lines and these
modified lines will be cast out.  It is therefore a requirement of
such a system to maintain a directory of such lines at the point when
they are granted their exclusive status and these lines considered as
modified even when they are not.  This directory will be called the
Exclusive.Cache.Directory (ECD) and the ECD will be accessed in
parallel with the L2 directory whenever a cache miss from an L1
occurs.  The total capacity of the L2 is the sum of the two
non-overlapping directories: ECD and the L2 Directory.  The directory
entry will specify which L1 cache has the line and whether the line
status is Exclusive or Read Only.  Adding lines to the ECD incurs the
same limitation associated with all cache directo...