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Use of a Small L2 as a Prefetch Buffer

IP.com Disclosure Number: IPCOM000106736D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 100K

Publishing Venue

IBM

Related People

Pomerene, J: AUTHOR [+2]

Abstract

Consider a memory hierarchy for a multiprocessing system in which eight processors each having a 128K L1 cache are supported by a single L2 whose capacity is 1 MB. Assume that the L1 caches are WI and modified lines that are replaced in the L1 must be cast-out as they are the sole valid copy of such lines. The requirement that the L2 contents be a superset over the L1 cache contents in such a configuration leaves the L2 with very little that is not present in one of the L1 caches. A better approach in such a limited L2 configuration is to provide for a greater flexibility in having information in the L2 that is not within the L1 caches. The desire is the use of the L2 as a prefetch buffer using the information that can be:

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Use of a Small L2 as a Prefetch Buffer

      Consider a memory hierarchy for a multiprocessing system in
which eight processors each having a 128K L1 cache are supported by a
single L2 whose capacity is 1 MB.  Assume that the L1 caches are WI
and modified lines that are replaced in the L1 must be cast-out as
they are the sole valid copy of such lines.  The requirement that the
L2 contents be a superset over the L1 cache contents in such a
configuration leaves the L2 with very little that is not present in
one of the L1 caches.  A better approach in such a limited L2
configuration is to provide for a greater flexibility in having
information in the L2 that is not within the L1 caches.  The desire
is the use of the L2 as a prefetch buffer using the information that
can be:

o   derived from the L3 miss addresses

o   derived by other information that the processors supply to a MMP
    - a processor attached to the L3.

o   derived from historical patterns of usage that were seen at the
    L3 from this requesting or other processors.

The basic idea is that by anticipating near-in future use the L2 can
effectively provide a means for reducing the time to service the L1
miss.

Lines in other L1 Caches - The usual way that the L2 is loaded as a
by-product of L1 misses will not provide for very many lines that are
in the L2 that are not currently in one of the L1.  If a means is
provided for a miss from an L1 to take advantage of a line that is
currently within another L1 cache then very little remains for an L2
loaded in the usual way to contain lines  that will service L1
misses.

      Every L1 miss that is either honored in the L2 or becomes an L3
access enters a processor that is attached to the L3 that is called
the Memory Management Processor (MMP).  It is the function of the MMP
to utilize the information that it can garner from the address of the
misses that it sees to prefetch for the L2 and when it prefetches
correctly and on a timely basis, the L1 miss will be an L2 hit as
opposed to an L2 miss.  The scope of the prefetching done by the MMP
is limited only by the information that is provided to it and working
merely with the L3 accesses ordered within processor and
distinguished as to Instruction/Data accesses, an expanded cache-like
structure can correlate these misses into prefetching opportunities.
Based on the access time characteristics of the L3 it may be
necessary for the information within the MMP to be chained before a
prefetch can be undertaken and the basic component of the MMP cache
must first be defined.  Only line not currently in the L2 are
prefetched.

Entry in the MMP Cache - The entry within the MMP cache links a
predecessor and successor L1-cache miss from a given processor
distinguished as either an I/D access.  Thus consecutive I-Misses
from the same processor and consecutive D...