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Reconfigurable Pipeline Sequence for RISC Processors Performance Modeling Tools

IP.com Disclosure Number: IPCOM000106738D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Kau, CC: AUTHOR [+2]

Abstract

RISC processors contain several pipeline stages to fetch, decode, dispatch, execute, and complete instructions. Depending on the organization, these stages may happen each in one cycle, less, or more.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 55% of the total text.

Reconfigurable Pipeline Sequence for RISC Processors Performance Modeling Tools

      RISC processors contain several pipeline stages to fetch,
decode, dispatch, execute, and complete instructions.  Depending on
the organization, these stages may happen each in one cycle, less, or
more.

      Writing a function for each phase and call it in the main loop
in the right order, causes the execution of that phase in one cycle.

      Suppose in a particular organization, fetch and decode happen
in one cycle, specifying this option when modeling this organization
should rearrange the function call sequence in the main loop
dynamically.  This is done by late binding in C using pointers.  That
is, pointer to functions instead of function names are used in the
main loop.  These pointers are assigned to various function names
during the run time as they are specified in the parameter file.

      To make each phase occur more than one cycle, intermediate
buffers to hold the instructions are used.

      For example, assume a processor has only FETCH, DISPATCH,
EXECUTE, and COMPLETE states indicated by F, D, E, and C.

Case1- each phase happens in one cycle:

        calling sequence in the main loop:

                        while more instructions do

                            C

                            E

                            D

       ...