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Browse Prior Art Database

Silicon Area Array via Structure

IP.com Disclosure Number: IPCOM000106747D
Original Publication Date: 1993-Dec-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Horton, RR: AUTHOR [+4]

Abstract

Increased I/O on the perimeter of a silicon MCM will drive flex pitch requirements that will be difficult to fabricate. It will also stretch the attachment process beyond present joining capabilities. Area arrays are a method of increasing I/O in the same package outline. The arrays can be placed on a grid that will allow placement to the next level to be made with ease. The array requires a via to allow connections to be made through the thickness of the carrier. A problem in making vias in a silicon substrate which is to be processed by POR BEOL techniques, would be the hole through the substrate and its effect on subsequent photoprocessing. An additional problem would be the isolation of the silicon substrate from the via. Disclosed is a process to put vias on a silicon substrate on a .

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This is the abbreviated version, containing approximately 52% of the total text.

Silicon Area Array via Structure

      Increased I/O on the perimeter of a silicon MCM will drive flex
pitch requirements that will be difficult to fabricate.  It will also
stretch the attachment process beyond present joining capabilities.
Area arrays are a method of increasing I/O in the same package
outline.  The arrays can be placed on a grid that will allow
placement to the next level to be made with ease.  The array requires
a via to allow connections to be made through the thickness of the
carrier.  A problem in making vias in a silicon substrate which is to
be processed by POR BEOL techniques, would be the hole through the
substrate and its effect on subsequent photoprocessing.  An
additional problem would be the isolation of the silicon substrate
from the via.  Disclosed is a process to put vias on a silicon
substrate on a .050 inch grid that would insulate each via from the
bulk silicon and allow for a minimum of a .035 inch diameter solder
ball connection.

      The process is described as follows.  The silicon substrate is
.025 inches thick <100> silicon.  It is thermally oxidized to .5
micrometers thick on both sides.  The substrate is to be
photoprocessed on the reverse side with a mask that will have open
areas .035 X .035 inches on
 .050 inch centers.  The mask will be aligned to the orientation mark
on the wafer to assure that the open squares are parallel to the
<100> crystal lattice.  After the resist is applied, baked, and
exposed, the wafer is immersed in a suitable solution such as HF to
remove the SiO2 exposed by the patterned resist.  The front side of
the wafer will have no resist and the SiO2 will be completely
removed.  The wafer is now processed to allow a .5 micrometer thick
blanket of Si3N4 to be applied to the front surf...